Related articles |
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SPARC compiler optimisation gregw@highland.oz.au (1992-02-13) |
Re: SPARC compiler optimisation casper@fwi.uva.nl (1992-02-14) |
Re: SPARC compiler optimisation how@leland.stanford.edu (1992-02-14) |
Re: SPARC compiler optimisation ucsd!math.ucla.edu!pmontgom@uunet.uu.net (1992-02-15) |
Re: SPARC compiler optimisation grunwald@foobar.cs.colorado.edu (1992-02-22) |
Re: SPARC compiler optimisation andrew@highland.oz.au (1992-02-26) |
Re: SPARC compiler optimisation dmk@craycos.com (1992-02-27) |
[4 later articles] |
Newsgroups: | comp.compilers,comp.sys.sun.misc |
From: | gregw@highland.oz.au (Greg Wilkins) |
Keywords: | optimize, sparc, question |
Organization: | Highland Logic |
Date: | Thu, 13 Feb 92 16:21:32 EST |
I need to generate frequent checksums on a SPARC machine, and I have
been looking at the code the sun optimizer produces for the code:
main()
{
int block[1000];
register int i;
register int xs=0;
for(i=999;i>0;i--)
xs|=*(block+i);
return xs;
}
The best that -O4 can do is a 5 tick loop:
L77010:
ld [%i5],%l3
dec 4,%i5
cmp %i5,%i3
bgu L77010
or %i4,%l3,%i4
where %i5 is set to block+999 and %i3 is block
It is possible to write a 4 tick loop (20% saving) :
LMYLOOP:
ld [%i3+%i5],%l3
deccc 4,%i5
bcc LMYLOOP
or %i4,%l3,%i4
where %i5 is i , and %i3 is block.
My question is why can the optimiser not generate this 4 tick loop?
The setup is simpler, the registers are the variables and
not combinations of the variables...
Looking at other code, it looks like the compiler/optimiser never
uses the [%R+%R] addressing mode. Is there a reason for this?
Does any other compiler do this? (I dont want to install gcc just to
answer this question).
Please email as well as post answers.
Greg Wilkins ( Software Manager ) @ Highland Logic
Snail : 46 Albany St, St Leonards, NSW, 2065, Australia
Email : gregw@highland.oz.au
Phone : (+61 2) 9066624 OR (+61 48) 683490
Fax : (+61 2) 4361540 OR (+61 48) 683474
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