Related articles |
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How Smart Can We Afford to be? jjones@uiuc.edu (1992-02-10) |
Re: How Smart Can We Afford to be? preston@dawn.cs.rice.edu (1992-02-12) |
Re: How Smart Can We Afford to be? metzger@bach.convex.com (1992-02-12) |
Re: How Smart Can We Afford to be? bill@hcx2.ssd.csd.harris.com (1992-02-13) |
Re: How Smart Can We Afford to be? idacrd!desj@uunet.uu.net (1992-02-24) |
Newsgroups: | comp.arch,comp.compilers |
From: | jjones@uiuc.edu |
Keywords: | architecture, design, question |
Organization: | University of Illinois, Dept. of Comp. Sci., Urbana, IL |
Date: | Mon, 10 Feb 1992 20:32:04 GMT |
Here are some thoughts/questions that have been mulling around in my head
since I took a class last year in "High-performance computer
architecture". Have at them.
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1. What is the rate of speed increase in transistor switching speeds?
2. How long does it take, on average, for a new semiconductor technology to
make it into a commerical product?
3. What is the difference in time to market of a non-pipelined RISC processor
with a large, simple on board cache/lots of registers and a heavily
pipelined, brach prediction, etc. processor?
4. How well do logical level designs for one technology transfer to another?
5. Can "smart" design systems aid the movement of a physical design from one
technology to another?
6. Can sophisticated optimizing compilers be built correctly in a timely
fashion?
7. What are the tradeoffs in writing a compiler that takes advantage of
lots of registers, versus a compiler that does a good job of instruction
scheduling and taking advantage of a pipeline?
--
Joel Jones, jjones@uiuc.edu
--
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