Request: YACC-able grammars for VHDL or Verilog

varghese@cs.MENTORG.COM (Joseph Varghese)
Mon, 27 Jan 92 17:56:34 PST

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Request: YACC-able grammars for VHDL or Verilog varghese@cs.MENTORG.COM (1992-01-27)
Re: Request: YACC-able grammars for VHDL or Verilog htf@castle.ed.ac.uk (H T Fallside) (1992-01-28)
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Newsgroups: comp.compilers
From: varghese@cs.MENTORG.COM (Joseph Varghese)
Keywords: yacc, question, VHDL
Organization: Compilers Central
Date: Mon, 27 Jan 92 17:56:34 PST

How can I get my hands on a YACC-able grammar for VHDL or Verilog? If you
don't know what VHDL and Verilog are, they are hardware description
languages that are used in the Electronic CAD industry. If these
languages have grammars that are not YACC-able, I would be interested in
knowing that. Or if you have implemented a compiler/translator for one of
these but cannot give me any sources, I would still be interested in
hearing from you.


Please respond by e-mail. If there is enough interest I will summarize.


Joe Varghese | varghese@mentor.com OR joe_varghese@mentorg.com
Mentor Graphics Corporation | (503) 685 7000 x2227
8005 SW Boeckman Road |
Wilsonville, OR 97070 |
[The last time someone asked, in 1989, no answers arrived. -John]
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