a code compactor

Hi,


We are developing a compactor for a DSP micro processor, a compactor is an
optimizer for an assembler which performs some machine specific
optimizations combined with clasical optimizations such as CSE,INV,SR,CP
and peephole. The compactor we are talking about performs a couple of
other special optimizations.


    1. Loop pipelining.


    2. Instruction Scheduling.


I have been entertaining the idea of using RTL as an intermediate language
for the assembler representation. e.g. Translating assembler source into
RTL and working on RTL instead of working on some proprietary intermediate
language. Although the intermediate language for our machine would be
simply a record of data that represented the target instructions directly.


Using the RTL system of GCC gives us many advantages.


      1. prior art.


      2. LARGE base of users.


      3. can pretty much represent machine with RTL completely as is.


      4. already many of the classical optimizations are written for us.


      5. The compactor will also work with a C compiler as a front end.


Disadvantages.


      1. RTL might be overkill for an assembler level optimizer.


      2. The reload pass and register allocator are separate passes.


      3. There is no provisions for multiple memory models
              architectures.


      4. The concept of parallel only comes into play at the last stage.




Any ideas are welcome.
--
marc.hoffman@analog.com
--

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