Re: Writing fast compilers...

glew@pdx007.intel.com (Andy Glew)
16 Aug 91 18:52:22 GMT

          From comp.compilers

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[2 earlier articles]
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| List of all articles for this month |
Newsgroups: comp.arch,comp.compilers
From: glew@pdx007.intel.com (Andy Glew)
In-Reply-To: miklg@sono.uucp's message of 15 Aug 91 20:59:12 GMT
Keywords: optimize, design
Organization: Intel Corp., Hillsboro, Oregon
References: <1991Aug15.205912.6553@sono.uucp>
Date: 16 Aug 91 18:52:22 GMT

        I am surprised that there has been some discussion of how much
        optimization should take place. IMHO, the more the better. In
        fact, the one optimization I haven't seen is that of figuring out
        that a particular value from a series of pointers (e.g.
        a->b->..->c[N]) is used several times and should be registered. I
        certainly can't do it in a declaration, so I end up just storing -
        temp = a->...c[N]. The overhead in retreiving a->b->..->c[N] is
        horrendous, and well worth a stupid "temp".


Common Subexpression Elimination should eliminate this sort of memory
reference chain - except that memory aliasing often makes it difficult
to tell if the value of a->b used in the chain a->b->c... has been
changed.


In the C environment, with parameter pointers all over the place, this
would require interprocedural analysis. Of course, most people don't
even do "global" analysis within a procedure to handle this sort of thing.


Separate compilation means that you have to worry about worst case
aliasing. One thing that I would like to see more of is compilation of
two (or more) versions of a procedure - one assuming maximum aliasing,
one assuming minimum aliasing. Which to use could be determined
statically: the compiler, when it generates a call, would say whether
the call had potentially aliased parameters or not, and the linker
would choose the appropriate version of the procedure. This
information could be propagated down the call tree. Or the information
could be used dynamically (for really big procedures).
--
Andy Glew, glew@ichips.intel.com
Intel Corp., M/S JF1-19, 5200 NE Elam Young Pkwy,
Hillsboro, Oregon 97124-6497
--


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