ASPLOS-IV Advance Program

Fourth International Conference on
Architectural Support for
Programming Languages
and Operating Systems


Santa Clara California
April 8-11 1991


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Monday, April 8


Tutorial I: "Compilation Techniques for Superscalar and VLIW Processors,"
Peter Hsu, Silicon Graphics, Mike Schlansker, Hewlett Packard


The next generation of processors will be using superscalar
and VLIW techniques to increase their performance. This tutorial will
cover the compiler techniques needed to exploit that parallelism.


Tutorial II: "How Future Technologies Will Affect Your Favorite Architecture,"
Howard Davidson, Sun Microsystems


Very dense silicon, very fast GaAs, and high performance
packaging can dramatically change the tradeoffs for implementing a new
system. These technologies will be described, and the implications
will be discussed.


----------------
Tuesday, April 9
Keynote Address: Forrest Baskett, Silicon Graphics, Inc.


Session I: Multiple Instructions Per Cycle Machines
Chairman: Norman Jouppi, Digital Equipment Corporation


"A Variable Instruction Stream Extension to the VLIW Architecture,"
Andy Wolfe,John P. Shen, Carnegie Mellon University
"Reducing the Branch Penalty by Rearranging Instructions in
  a Double-Width Memory,"
Manolis Katevenis, Nestoras Tzartzanis, FORTH, Crete, Greece
"The Floating Point Performance of a Superscalar SPARC Processor,"
            Roland L. Lee, Alex Kwok, Sun Microsystems, Faye Briggs, Tandem Computers


Session II: Cache Conscious Designs
Chairman: George Taylor, Sun Microsystems


"Software Prefetching,"
"David Callahan, Ken Kennedy, Allan Porterfield," Tera Computer Company
"High-Bandwidth Data Memory Systems for Superscalar Processors,"
Gurindar Sohi, Manoj Franklin, University of Wisconsin, Madison
"The Cache Performance and Optimizations of Blocked Algorithms,"
Monica Lam, Edward E. Rothberg, Michael E. Wolf, Stanford University
"The Effect of Context Switches on Cache Performance,"
Jeffrey C. Mogul, Anita Borg, Digital Equipment Corporation


Session III: Architectural Support For Operating Systems
Chairman: Joel Emer, Digital Equipment Corporation


"A Portable Interface for On-the-Fly Instruction Space Modification,"
David Keppel, University of Washington
"Virtual Memory Primitives for User Programs,"
Andrew W. Appel, Kai Li, Princeton University
"The Interaction of Architecture and Operating System Design,"
Thomas E. Anderson, Henry M. Levy, Brian N. Bershad,
Edward D. Lazowska, University of Washington


Evening Panel Session:
"An OS Perspective: Criticisms of RISC/ Beyond 32-Bit Addressing"


Topics include why operating systems arenUt getting as fast
as RISCs, whether segmentation will return with 64-bit address, and
specific instruction set complaints. Complimentary local beers, wine,
and hors d'oeuvres.


----------------
Wednesday, April 10


Session IV: Architectural Support For Programming Languages
Chairman: Guy Steele, Thinking Machines Corporation


"Integrated Register Allocation and Instruction Scheduling for RISCs
David G. Bradlee, Susan J. Eggers, Robert R. Henry,
University of Washington
"Code Generation for Streaming: an Access/Execute Mechanism,"
Manuel E. Benitez, Jack W. Davidson, University of Virginia
"Efficient Implementation of High Level Parallel Programs,"
Rajive Bagrodia, Sharad Mathur, University of California, Los Angeles


Session V: Instruction-Level Parallelism
Chairman: James Smith, Cray Research


"Vector Register Design for Polycyclic Vector Scheduling,"
William Mangione-Smith, Santosh G. Abraham, Edward Davidson,
University of Michigan
"Fine-grain Parallelism with Minimal Hardware Support:
  A Compiler-Controlled Threaded Abstract Machine,"
David E. Culler, Anurag Sah, Thorsten von Eicken, John Wawrzynek,
University of California, Berkeley
"Limits of Instruction-Level Parallelism,"
David W. Wall, Digital Equipment Corporation


Session VI: I/O and Operating Systems
Chairman: David A. Patterson, University of California, Berkeley


"Performance Consequences of Parity Placement in Disk Arrays,"
Edward K. Lee, Randy H. Katz, University of California
"Combining the Concepts of Compression and Caching for a Two-Level Filesystem,"
Vincent Cate, Thomas Gross, Carnegie Mellon University
"NUMA Policies and Their Relation to Memory Architecture,"
William J. Bolosky, Michael L. Scott, Robert P. Fitzgerald,
Robert J. Fowler, Alan L. Cox, University of Rochester


Session VII: Architectural Support For Multiprocessors
Chairman: Mark Hill, University of Wisconsin, Madison


"LimitLESS Directories: A Scalable Cache Coherence Scheme,"
David Chaiken, John Kubiatowics, Anant Agarwal,
Massachusetts Institute of Technology
"An Efficient Cache-based Access Anomaly Detection Scheme,"
Sang Lyul Min, Jong-Deok Choi, IBM T.J. Watson Research Center
"Performance Evaluation of Memory Consistency Models
  for Shared Memory Multiprocessors,"
Kourosh Gharachorloo, Anoop Gupta, John Hennessy, Stanford University


Evening Panel Session: "The Dead Computer Society"


(Including autopsies of Cydrome, Multiflow....)
Complimentary local beers, wine, and hors d'oeuvres.


----------------
Thursday, April 11




Session VIII: Multiprocessors and Memory Management
Chairman: William Dally, Massachusetts Institute of Technology


"Process Coordination with Fetch-and-Increment,"
Eric Freudenthal, Allan Gottlieb, New York University
"Synchronization without Contention,"
John M. Mellor-Crummey, Rice University
Michael L. Scott, University of Rochester
"The Case for a Read Barrier,"
Douglas Johnson, Texas Instruments


Session IX: Quantitative Analysis of RISCs
Chairman: Martin Hopkins, IBM


"An Analysis of MIPS and SPARC Instruction Set Utilization
  on the SPEC Benchmarks,"
R.F. Cmelik, S.I. Kong, Dave Ditzel, E. Kelly, Sun Microsystems
"Performance Characteristics of Architectural Features
  of the IBM RISC System/6000,"
C. Brian Hall, Kevin O'Brien, IBM Canada Ltd.
"Performance from Architecture:
Comparing a RISC and a CISC with Similar Hardware Organization,"
Dileep Bhandarkar, Digital Equipment Corporation
Douglas W. Clark, Harvard University


----------------
Conference Chairs
General Bob Rau Hewlett-Packard
Program Dave Patterson U.C. Berkeley
Treasurer Dave Yen Sun Microsystems
Publicity Allen Baum Apple Computer
Local Arrangements Bhadrik Dalal Amdahl Corp.
Registration Danny Low Hewlett-Packard


Program Committee
Dave Patterson U.C. Berkeley (chairman)
Bill Dally MIT
Dave Ditzel Sun Microsystems
Joel Emer DEC VAX Engineering
Mark Hill University of Wisconsin
Marty Hopkins IBM
Douglas Johnson Texas Instruments
Norm Jouppi DEC Western Research
Manolis Katevenis Research Center of Crete
Monica Lam Stanford University
Hank Levy University of Washington
Mahadev Satyanarayan Carnegie Mellon Univ.
Jim Smith Cray Research
Guy Steele Thinking Machines Corp.
George Taylor Sun Microsystems


Registration


Conference registration includes one copy of the proceedings, lunches,
and snacks at breaks. Tutorial registration covers both tutorials and
includes one copy of notes for each tutorial, a lunch, and snacks at
breaks. For further information, contact Lynn Dochterman at (415)
857-5911 or asplos@hplabs.hp.com Conference Site All technical
sessions, lunches, and registration will be held at the Doubletree
Hotel at Santa Clara, 5101 Great America Parkway, Santa Clara,
California, telephone (408) 986-0700.


As is customary for ASPLOS, there will be panel sessions in the
evenings on controversial and/or topical subjects. This year there
will be panels both Tuesday and Wednesday evenings. In addition to
listening to interesting speakers, ASPLOS-IV attendees will be able to
sample complimentary beer from local microbreweries, California wines,
and hors d'oeuvres.


Transportation


San Jose International Airport is approximately five miles from the
Doubletree Hotel. The hotel has a shuttle that runs to the airport
every half hour. The hotel is about 45 minutes south of San Francisco
International Airport and is accessible by airport limousine for about
$20.


United Airlines has been designated the official carrier of ASPLOS-IV
offering special round-trip fares to North American conferees. United
and United Express will allow an additional 5% saving off any
published fare within the United States, or, with seven days' advance
purchase, 45% off full coach fare from domestic cities or comparable
published Canadian Meeting Fares from selected Canadian cities. These
fares are valid from April 4 through April 14, 1991. To take advantage
of these discounts, call (800) 521-4041 and cite Meeting ID No. 4490D,
or give this information to your local travel agent.


Climate


The weather in Santa Clara in April is sunny, with occasional foggy
mornings. Temperatures range from the low 50's F on foggy mornings
to the low 70's F during the day. A light jacket may be needed in
the early morning and evening. Rain is fairly unlikely. Casual
attire is appropriate throughout the conference.


----------------------------------------------------------------


ASPLOS-IV Registration Form
---> Note: This registration form can be used <---
---> for registration by mail, fax, or email. <---


ASPLOS-IV
Hewlett-Packard 3U-7
P.O. Box 10490
Palo Alto, CA 94303-0969
(415) 857-5911; Fax: (415) 857-8558; Email: asplos@hplabs.hp.com


Name: ________________________________________________
Affiliation: ________________________________________________
Address: ________________________________________________
________________________________________________
Phone: ________________


          __ACM __ ACM SIGARCH __ IEEE Member no.: ____________
Electronic mail address: ________________________________


(Before March 1)
Member Non-Member Student
Symposium __ $245 __ $295 __ $120
Tutorial __ $145 __ $195 __ $85


(After March 1)
Member Non-Member Student
Symposium __ $290 __ $350 __ $120
Tutorial __ $195 __ $245 __ $85




__ Check drawn on U.S. bank payable to: ASPLOS-IV
__ Master Card __ Visa __ American Express


Card no.: ________________
Expiration date: ________
Name on card: ________________________________
Signature: ________________________________


----------------------------------------------------------------


ASPLOS-IV Hotel Registration Form




Doubletree Hotel at Santa Clara
5101 Great America Parkway
Santa Clara, California 95054
(408) 986-0700; Fax: (408) 986-1584




Name: ________________________________________________________________
Address: ________________________________________________________________


Phone: ________________________________
Arrival date & time: ________________
Departure date: ________________


Reservations must be received by March 10, 1991.


__ Single $92 __ Double $92
(8% State tax not included)


__ Master Card __ Visa __ Diners Club


Card no.: ________________
Expiration date: ________
Name on card: ________________________________
Signature: ________________________________


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