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| Register Allocation and Aliasing aglew@oberon.crhc.uiuc.edu (1990-07-05) |
| Re: Register Allocation and Aliasing rfg@ncd.com (1990-07-06) |
| Re: Register Allocation and Aliasing preston@rice.edu (Preston Briggs) (1990-07-14) |
| Re: Register Allocation and Aliasing pur-ee!hankd@dynamo.ecn.purdue.edu (1990-07-14) |
| Re: Register Allocation and Aliasing torbenm@diku.dk (1990-07-14) |
| Re: Register Allocation and Aliasing mike@vlsivie.at (1990-07-15) |
| Re: Register Allocation and Aliasing aglew@dwarfs.crhc.uiuc.edu (1990-07-16) |
| Re: Register Allocation and Aliasing phorgan@cup.portal.com (Patrick Horgan) (1990-07-17) |
| Re: Register Allocation and Aliasing heggy@cs.pitt.edu (1990-07-17) |
| Re: Register Allocation and Aliasing aglew@oberon.crhc.uiuc.edu (1990-07-17) |
| Re: Register Allocation and Aliasing lupine!rfg@uunet.UU.NET (1990-07-19) |
| Re: Register Allocation and Aliasing lupine!rfg@uunet.UU.NET (1990-07-19) |
| Re: Register Allocation and Aliasing vestal@src.honeywell.com (1990-07-19) |
| Newsgroups: | comp.compilers |
| From: | Patrick Horgan <phorgan@cup.portal.com> |
| Keywords: | code, optimize |
| Organization: | Compilers Central |
| Date: | Tue, 17 Jul 90 12:40:57 GMT |
On Amdahl machines a data read or write to cache or register takes only
one cycle. There is no difference.
Patrick Horgan phorgan@cup.portal.com
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