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[19 earlier articles] |
Re: Register allocation rgd00@doc.ic.ac.uk (Rob Dimond) (2005-05-16) |
Re: Register allocation torbenm@diku.dk (2005-05-18) |
Re: Register allocation thibault.langlois@di.fc.ul.pt (thibault.langlois@di.fc.ul.pt) (2005-05-20) |
Re: Register allocation c3riechers@adelphia.com (Chuck Riechers) (2005-05-21) |
register allocation camille@bluegrass.net (David Lindauer) (2005-11-12) |
register allocation dgb@cs.washington.edu (1989-11-22) |
Re: register allocation larus@primost.wisc.EDU (1989-11-24) |
Register Allocation napi@rangkom.MY (1990-02-17) |
Re: Register Allocation cik@l.cc.purdue.edu (1990-02-15) |
Re: Register Allocation wendyt@cs.washington.edu (1990-02-26) |
Re: Register Allocation Moss@cs.umass.edu (1990-02-25) |
Re: Register Allocation dds@cc.ic.ac.uk (1990-02-27) |
Register Allocation nandu@jupiter.cs.clemson.edu (1993-03-31) |
[3 later articles] |
From: | larus@primost.wisc.EDU (James Larus) |
Newsgroups: | comp.compilers |
Keywords: | chow, chaitin |
Date: | 24 Nov 89 18:36:16 GMT |
References: | <1989Nov22.183501.6735@esegue.segue.boston.ma.us> |
Organization: | University of Wisconsin--Madison |
Just a note on Bob Scheulen's (microsoft!bobs@beaver) article. There's no
reason why Chow's algorithm can't be post-generation (i.e., allocate register
for the actual instruction set). I used it that way in the SPUR Lisp compiler.
Of course, assembly code for RISC machines looks a lot like intermediate code.
/Jim
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