Instruction Scheduling

bron@bronze.wpd.sgi.com (Bron Campbell Nelson)
Wed, 5 Jul 89 11:34:08 PDT

          From comp.compilers
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Date: Wed, 5 Jul 89 11:34:08 PDT
From: bron@bronze.wpd.sgi.com (Bron Campbell Nelson)

Rajeev Chandrasekhar of Intel asked for articles on Instruction Scheduling.
I thought there might be some general interest in the topic, so thought
I'd send my list to comp.compilers. These are papers I've found interesting,
along with my own biased comments.




Thomas Gross, "Code Optimization of Pipeline Constraints",
technical report #83-255, dec 1983
Computer Systems Lab, EECS, Stanford University, Stanford CA.
(or his PhD thesis which is more or less the same; I don't
have the reference).
This is the technology that MIPSco instruction re-ordering
is (or at least was originally) based on.


Gibbons and Muchnick, "Efficient Instruction Scheduling for
a Pipelined Architecture", SIGPLAN Compiler Construction
proceedings, 1986.
The HP Precision Architecture. Strongly based on Gross's work.


J.R. Ellis, "Bulldog: A Compiler for VLIW Architechtures," PhD
thesis, Yale University. Also published by MIT press as part
of the ACM Doctoral Disertation Award Series.
The definitive work on trace scheduling. Used by Multiflow.




Rajiv Gupta and Mary Lou Soffa, "Region Scheduling" Proceedings
of the 2nd International Conf. on Supercomputing, 1987.
Refinements on the idea of trace scheduling. The paper descibes
work in progress, not demonstrated technology, but it looks to
have promise.


Wei-Chung Hsu, "Register Allocation and Code Scheduling for Load/Store
Architectures", PhD thesis, University of Wisconsin - Madison,
1987.
A good integration of earlier works. Tries to deal with the
interdependency of register allocation and code scheduling.




--
Bron Campbell Nelson
bron@sgi.com or possibly ..!ames!sgi!bron
--

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