Re: UNCOL issues

In article <3890@ima.ima.isc.com> mark@hubcap.clemson.edu (Mark Smotherman) writes:
>I'd be interested in how folks see the DARPA CORE ISA (i.e. essentially
>a Stanford MIPS assembly language standard as intermediate code with
>optimizing assemblers underneath) as just another version of the UNCOL
>ambitions.
>-----
>Mark Smotherman, Comp. Sci. Dept., Clemson University, Clemson, SC 29634
>INTERNET: mark@hubcap.clemson.edu UUCP: gatech!hubcap!mark
>[I was under the impression that the core isa was targeted at a relatively
>narrow class of target machines, which makes the problem a lot easier. Someone
>better informed than me could probably clarify this. -John]


CORE ISA (which has some very non-RISCy instruction like FPSQRT in
it, and 64-bit 2-register instructions) is NOT another UNCOL attempt. It
was targeted to be the target for a (small) number of stanford MIPS-like
RISC CPUs. The CPUs were designed specifically to run CORE efficiently after
translation (before assembly). The purpose of this is to create a family
of processors from GaAs to CMOS that use the same compilers, and thus save
money for the government, and make it somewhat easier to develop and test
software on CMOS chips meant for blazingly fast and expensive GaAs systems.


You can even write in assembler (CORE) and not have to rewrite it
for the GaAs chips.
[From jesup@cbmvax.cbm.commodore.com (Randell Jesup)]
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