Compilers for Decoupled Architectures.

I am interested in references on compilers for decoupled architectures and
machines with a similar register structure (such as the CDC 170 and the Crays).


A decoupled CPU consists of two or more processors which each read the
instruction stream at their own rate. Typically there is one
processor for address calculation and another for other calculations.
The idea is that the address calculation processor will typically be
farther ahead in the instruction stream, than the other processors
and so can request loads well in advance of the time the data is needed
by the other processors. The processors communicate with each other and
with the memory interface only through fifo queues.


In order to minimize communication from the integer calculation processor
to the address calculation unit (such communication forces the address
processor to stop until the integer processor has caught up and is hence
undesirable), the register set is split into (at least) index registers,
which reside in the address processor, and data registers which reside
in the other processors. This in much like the 170 with its B (index)
and X (data) registers, and the Cray with its B (index) and, S and T (data)
registers. This presents an interesting register allocation problem.
E.g. Given a loop
for( i = 0 ; i < N ; ++i ) {
A[i] = B[i] + z ;
}
It is best to allocate i and N index registers and A[i], B[i], and z to
data registers. To make matters worse, the width of the index registers
may be less than the width of data registers so that they may not hold
an entire C int or Fortran integer.


Any pointers to literature discussing this sort of problem would be
greatly appreciated, as would comments from people who have looked
at this sort of problem.


norvell@csri.toronto.edu
or {utzoo, decvax, ...}!utcsri!norvell


Theo Norvell
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