Re: Real Compiler for One Instruction Computer?

Actually, I own a REAL HARDWARE OISC according to van der Poel. It runs
(crawls would be a better word) the PL0 high level language (a Pascal subset).


Its origin is immaterial, suffice it to say that some very bright and very
fanatic people put the hardware together in 1987 in the Netherlands, just for
fun, and decided to show that it could do everything that a computer was
supposed to do, by writing an interpreter for the PL0 virtual machine [Wirth
1976] for the 'van der Poel' instruction set. I am the 'caretaker' of the
machine.


The actual machine is a single board, designed to operate at a reasonably high
clock speed (I believe 12 MHz), using fast static RAM as main memory. The only
I/O of the 'computer' is a double UART, to hook it between an Atari/ST and a
terminal. The ST does the translation of the Pascal subset (PL0 from Wirth's
book 'Algorithms + Data Structures = Programs') to the PL0 virtual machine
code. There is no reason why the compiler couldn't be made to run on the OISC,
other than the fact that the current OISC board has a limited amount of
main memory and lacks file I/O devices (besides the obvious SPEED problem).


The whole thing was a fun exercise, but the actual machine runs and does its
job, hence showing once and for all that 'van der Poel' was right (of course).


However, don't think of this as the ultimate RISC. RISC is a carefull balance
of what to do in hardware and what to do in software - not a minimization of
the opcode set. The van der Poel machine is VERY SLOW on any task, given its
memory bandwidth, due to the fact that doing any computation at all requires
just too many instructions.


    just thought I'd mention that it CAN and HAS BEEN done,


    Gert Slavenburg
    (UUCP : ..!pyramid!prls!gert)


[Wirth 1976] N. Wirth, 'Algorithms + Data Structures = Programs', Prentice Hall
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