PALM challenge

Steve Lewis <>
Sat, 1 Oct 2022 01:24:20 -0700 (PDT)

          From comp.compilers

Related articles
PALM challenge (Steve Lewis) (2022-10-01)
Re: PALM challenge (gah4) (2022-10-01)
Re: PALM challenge (Thomas Koenig) (2022-10-02)
Re: PALM challenge (gah4) (2022-10-03)
| List of all articles for this month |

From: Steve Lewis <>
Newsgroups: comp.compilers
Date: Sat, 1 Oct 2022 01:24:20 -0700 (PDT)
Organization: Compilers Central
Injection-Info:; posting-host=""; logging-data="25624"; mail-complaints-to=""
Keywords: history, architecture, comment
Posted-Date: 01 Oct 2022 15:16:21 EDT

Lots of new CPUs, sure.

But let's explore an old CPU: the 1975 PALM.

I'm looking for anyone interested to explore the idea. Maybe prove how
robust modern tools are at adapting C, by exploring this ancient instruction

You won't find much about this instruction set. But, we've found an internal
IBM documentation about it. We have an emulator for it. And we have an
assembler for it.

I'm no expert about this process, hence seeking help. From what I understand,
the instruction set has 4 tiers of 32 registers. Each tier is an interrupt
level. In Level 0, the first register holds the program counter (and the
second register is reserved as a branch target for certain branch
instructions- other than that, I think the registers are all fair game).
There are no Index registers, and no Overflow/Underflow registers (that I'm
aware of). There is a special instruction for accessing some Devices (so
retaining the option for some inline assembly would good - these may be
necessary for keyboard and screen output). In total it is approximately 45

[Architecture described here
It doesn't look like it would be all that bad as a target for C although the code to handle the stack
might be a bit tedious. -John]

Post a followup to this message

Return to the comp.compilers page.
Search the comp.compilers archives again.