Re: C compiler pointer management on DSPs

robin51@dodo.com.au
Fri, 28 Feb 2020 10:26:48 +1100

          From comp.compilers

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[5 earlier articles]
Re: PR1ME C compiler sources gneuner2@comcast.net (George Neuner) (2019-09-27)
Re: C compiler pointer management on DSPs derek@_NOSPAM_knosof.co.uk (Derek M. Jones) (2019-09-28)
Re: C compiler pointer management on DSPs david.brown@hesbynett.no (David Brown) (2019-09-29)
Re: C compiler pointer management on DSPs 847-115-0292@kylheku.com (Kaz Kylheku) (2019-09-30)
Re: C compiler pointer management on DSPs gneuner2@comcast.net (George Neuner) (2019-10-03)
Re: C compiler pointer management on DSPs gah4@u.washington.edu (2020-02-27)
Re: C compiler pointer management on DSPs robin51@dodo.com.au (2020-02-28)
Re: C compiler pointer management on DSPs gah4@u.washington.edu (2020-02-28)
| List of all articles for this month |
From: robin51@dodo.com.au
Newsgroups: comp.compilers
Date: Fri, 28 Feb 2020 10:26:48 +1100
Organization: Compilers Central
References: 19-09-003 19-09-004 19-09-006 19-09-007 19-09-009 19-09-015 19-09-017 19-09-018 20-02-024
Injection-Info: gal.iecc.com; posting-host="news.iecc.com:2001:470:1f07:1126:0:676f:7373:6970"; logging-data="46377"; mail-complaints-to="abuse@iecc.com"
Keywords: architecture
Posted-Date: 27 Feb 2020 22:03:25 EST
In-Reply-To: 20-02-024

On 2020-02-28 09:23, gah4@u.washington.edu wrote:


> Machines not so well designed require masking off the appropriate
> bits before operating with them, though many machines ignore high
> bits on shift operations. (The 8086 allows shifts up to 255 bits.)


Who can say that the CDC machines (7600; 70 series, etc) were not
well designed?


They were intended to be fast, and to carry out operations on
words (of 60 bits).


To be sure, it was necessary to mask bits (usually characters),
but there was a simple instruction(s) to generate a mask of
n bits (better than loading a word containing bits to be used
as a mask).


On the other hand, the IBM S/360 was designed from the beginning to
handle bytes of 8 bits, half-words of 16 bits, and words of 32 bits.


Instructions could load and store a byte into/from the low-order
bits of a register, without affecting the other bits. Later models
could load/store one or more bytes into/from a register without
affecting the other bits.


For more general work, masking operations were available in the
32-bit registers.


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