Re: Unum numbers

Hans-Peter Diettrich <>
Wed, 18 Apr 2018 10:50:25 +0200

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Unum numbers (Hans-Peter Diettrich) (2018-04-12)
Re: Unum numbers Pidgeot18@verizon.invalid (=?UTF-8?Q?Joshua_Cranmer_=f0=9f=90=a7?=) (2018-04-12)
Re: Unum numbers (Hans-Peter Diettrich) (2018-04-18)
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From: Hans-Peter Diettrich <>
Newsgroups: comp.compilers
Date: Wed, 18 Apr 2018 10:50:25 +0200
Organization: Compilers Central
References: 18-04-043 18-04-053
Injection-Info:; posting-host=""; logging-data="90772"; mail-complaints-to=""
Keywords: arithmetic
Posted-Date: 19 Apr 2018 01:19:54 EDT
In-Reply-To: 18-04-053

Am 13.04.2018 um 05:13 schrieb Joshua Cranmer 🐧:

> I understand that the newest proposal returns to fixed-width size.

This and further simplifications IMO didn't make the last (Posit)
variant much more practical. At least had I moved the variable-sized
Regime bitfield to the end of the number, so that exponent and
fraction keep starting at fixed bit positions. In a hardware
implementation this modification will save some shift cycles in the
compression and expansion between the external Posit format and the
internal quire registers.

> Beyond that, the only thing I really know about unums is that their
> inventor claims them and interval arithmetic to eliminate the need for
> numerical analysts, which is contested by one of the leads of the IEEE
> 754 standard, and I'm not really qualified to comment on this debate.

For Posit numbers of 32 bit size the author suggests a quire register
size of at least 256 bit, which is much larger than the 83 bit
accumulator in the IEEE hardware. For 64 bit size 512 bytes are
suggested as a minimum, and for full IEEE "double" compatibility with
11 exponent bits a size of 524288 bits is suggested. So many register
bits may help with certain numerical problems in computations, but not
when afterwards a result is stored in 64 bits again. E.g. the external
format requires at least 11 bits for the representation of all
integral numbers up to 64, with 3 more bits for every next quadruple
integer (1 regime bit, 2 fraction bits).

I'm too lazy to write a simulation of both the Posit and a super size
IEEE implementation, so that the presented benchmark codes could be
compared when calculated with the same quire register size.


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