Maximal Munch instruction selection: how to connect tiles?

=?UTF-8?B?Q8Opc2Fy?= <divcesar@gmail.com>
Mon, 28 Sep 2015 15:56:17 -0300

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Maximal Munch instruction selection: how to connect tiles? divcesar@gmail.com (=?UTF-8?B?Q8Opc2Fy?=) (2015-09-28)
Re: Maximal Munch instruction selection: how to connect tiles? DrDiettrich1@netscape.net (Hans-Peter Diettrich) (2015-09-29)
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From: =?UTF-8?B?Q8Opc2Fy?= <divcesar@gmail.com>
Newsgroups: comp.compilers
Date: Mon, 28 Sep 2015 15:56:17 -0300
Organization: Compilers Central
Keywords: optimize, question
Posted-Date: 28 Sep 2015 15:36:23 EDT

Given the expression a = b + c; my compiler currently produces the
following IR-tree:


        =
    / \
a + (_t1)
              / \
          b c


that is, it assumes:
- an assignment operator that copy from a register (_t1) to a memory (a);
- an add operator that sum the content of two memory regions (b and c)
and put the result in a register (_t1).


I am trying to use the maximal munch strategy to produce assembly code
for this tree but I'm stuck with the following questions:


1) The '=' operator assume the right hand side expression to be in a
register; what happens if that turn out to be impossible? I.e., what
happens if there is no '+' instruction that put the result in a
register.


2) Consider that there is no '+' instruction that can sum two memory
regions but there is one that can sum two registers. How can I make
use of the later instruction? I imagine that I should use loads to
move the variables to registers and later connect the '+' instruction
to these registers. But in that case, should the tree be modified to
reflect that change?


3) Is there any text with a complete and formal description of the
Maximal Munch IS algorithm?
[Appel's Modern Compiler Implementation in <x> has a description and sample
code, but it doesn't look like it'd be very helpful here. I'd suggest adding
more nodes to your tree to make it easier for instruction patterns to match,
e.g., start with a tree that pretends every value will be loaded into a
register, and if your ISA has memory to register ops, the instruction patterns
match some of the loads and you can then forget about the registers that
the matched loads didn't use:


          =
    / \
a + (_t1)
              / \
            _t2 _t3
              | |
              b c


-John]



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