Verilog simulator/flow graph compiler position

Steve Meyer <>
Sat, 24 Mar 2012 08:43:44 -0800

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Verilog simulator/flow graph compiler position (Steve Meyer) (2012-03-24)
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From: Steve Meyer <>
Newsgroups: comp.compilers
Date: Sat, 24 Mar 2012 08:43:44 -0800
Organization: Compilers Central
Posted-Date: 26 Mar 2012 04:16:57 EDT

Tachyon Design Automation based in Minneapolis MN is looking for
another computer science type to work with two other scientists on our
CVC Verilog HDL simulator in the Electronic Design Automation (EDA) digital
circuit design area. Job requires at least a masters degree and
knowledge of flow graph compiler algorithms. Verilog requires both
very low level parallel operations for procedural simulation and also more
conventional logic gate simulation operations. Our develop methods
and programs follow Peter Naur's anti-formalist dataology methodology.

Tachyon is run like a scientific lab where every developer works on all areas
of Verilog EDA tools currently simulation and compilation. In addition to
continual bug fixing (the Verilog specification drifts slightly), some
sample tasks are: developing high level Verilog 4 state value tracking,
improving low level machine code sequences, implementing new Common Power
Format (CPF) support, developing a virtual machine for new X value
propagation checking simulation. Position also involves internal CVC
algorithm and code simplifying rewriting, and writing and presenting research

CVC is the fastest available Verilog simulator. Tele-commuting or consulting
might be possible provided travel to Minneapolis is reasonable.

See our web site for more information on CVC and Tachyon DA.

No agencies or phone calls.

If interested, send email to me (Steve Meyer)

Steve Meyer
Tachyon Design Automation Corp.
80 South 8th Street, Suite 900
Minneapolis, MN 55402

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