Call For Papers - 4th Workshop on Architectural and Microarchitectural Support for Binary Translation

CALL FOR PAPERS -- AMAS-BT 2011


4th Workshop on Architectural and Microarchitectural Support for
Binary Translation


Held in conjunction with the 38th Int'l Symposium on Computer
Architecture (ISCA-38)


San Jose, California, USA -- June 4, 2011


http://amas-bt.cs.virginia.edu/


Workshop Overview


Long employed by industry, large scale use of binary translation and
on-the-fly code generation is becoming pervasive both as an enabler
for virtualization, processor migration and also as processor
implementation technology. The emergence and expected growth of just-
in-time compilation, virtualization and Web 2.0 scripting languages
brings to the forefront a need for efficient execution of this class
of applications. The availability of multiple execution threads brings
new challenges and opportunities, as existing binaries need to be
transformed to benefit from multiple processors, and extra processing
resources enable continuous optimizations and translation.


The main goal of this half-day workshop is to bring together
researchers and practitioners with the aim of stimulating the exchange
of ideas and experiences on the potential and limits of Architectural
and MicroArchitectural Support for Binary Translation (hence the
acronym AMAS-BT). The key focus is on challenges and opportunities for
such assistance and opening new avenues of research. A secondary goal
is to enable dissemination of hitherto unpublished techniques from
commercial projects.


The workshop scope includes support for decoding/translation, support
for execution optimization and runtime support. It will set a high
scientific standard for such experiments, and requires insightful
analysis to justify all conclusions. The workshop will favor
submissions that provide meaningful insights, and identify underlying
root causes for the failure or success of the investigated technique.
Acceptable work must thoroughly investigate and communicate why the
proposed technique performs as the results indicate.


Submission Topics


Hardware assistance for translation and code discovery:


Interpretation engines, decoding assistance, translated code dispatch
On-the-fly reconstruction of CFGs and data dependences, scheduling and
optimization
Bug-per-bug compatibility issues
Static translation: without runtime assistance/translation and with
runtime assistance/translation (Hybrid Translation)
Hardware assistance for optimization:


Extra/enhanced internal/physical registers
Speculative execution support
Reduced footprint/low-power cores enabled by binary translation, area
and power efficiency
Techniques for parallelizing single-thread programs
Hardware assistance for runtime management:


Self-modifying code, self-referential code, precise exceptions
Runtime information: profiling branch directions, instructions with
cache misses, memory access monitoring
Management of translated code and adapting code to changing program
behavior, persistent translation, incremental translation
Multi-many cores: parallel translation, auto parallelization,
speculative execution
Binary Translation: Architectural effects and experience:


Novel applications of binary translation and virtualization
Performance characterization
Dynamic instrumentation and debugging
HW/SW co-design for efficient execution
Experimental insights on binary translation and industrial experience
How to Submit


In order to submit a paper to AMAS-BT 2011 authors should use
EasyChair.
See https://www.easychair.org/conferences/?conf=amasbt2011
If you do not already have an EasyChair account, you can generate one
using the same link. Click on New Submission, and then follow the
instructions to submit your paper. You can return later to update your
submission. EasyChair will send you an e-mail message confirming your
submission. Please remember that AMAS-BT 2011 uses a two phase
submission process. You will first submit the abstract of your paper,
and later the final manuscript (please check the important dates
below). Submissions should be ready for publication, containing no
more than 5000 words, in IEEE style, 2-column, 10-point text
using .doc, .pdf, or .ps. formats.
Important Dates


Abstract due: April 18, 2011
Submission: April 25, 2011
Notification of acceptance: May 2, 2011
Workshop Organizers


Mauricio Breternitz, AMD
Robert Cohn, Intel
Erik Altman, IBM
Youfeng Wu, Intel
Program Committee


Erik Altman, IBM
Guido Araujo, UNICAMP
Edson Borin, UNICAMP
Mauricio Breternitz, AMD
Mark Charney, Intel
Josep M. Codina, Intel
Robert Cohn, Intel
Andy Glew, Intel
Kim Hazelwood, University of Virginia
David Kaeli, Northeastern University
Chris J. Newburn, Intel
Suresh Srinivas, Intel
Chenggang Wu, CAS, China
Youfeng Wu, Intel

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