Re: Results from Cache simulator

glen herrmannsfeldt <gah@ugcs.caltech.edu>
Sun, 6 Mar 2011 09:34:06 +0000 (UTC)

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Related articles
Results from Cache simulator weili747@gmail.com (Wei Li) (2011-03-04)
Re: Results from Cache simulator gneuner2@comcast.net (George Neuner) (2011-03-05)
Re: Results from Cache simulator gah@ugcs.caltech.edu (glen herrmannsfeldt) (2011-03-06)
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From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Newsgroups: comp.compilers
Date: Sun, 6 Mar 2011 09:34:06 +0000 (UTC)
Organization: A noiseless patient Spider
References: 11-03-007
Keywords: architecture
Posted-Date: 06 Mar 2011 13:44:43 EST

Wei Li <weili747@gmail.com> wrote:


> I am using a cache simulator for my research on loop tile selection
> problem. My understanding is that for a given input, I should have the
> same result. No matter how many time I repeat that experiment.
> However, I am getting a slightly different result. For example, in one
> run I got 153265565 read misses and in another run with the same data
> I got 153266725. What is the reason for this difference?


As I remember it, when IBM did the research leading up to the 360/85,
(the first machine with cache), they had instruction traces.


That is, lists of instructions and operand addresses (and maybe
operand values) of actual running programs. Given the trace,
you can study different cache configurations. The cache should
change the speed, but not the instruction order (for user mode).
You only run the simulator once, but use the results many times.


(In supervisor mode, it might change interrupt timing, which could
then change the instruction mix, and affect the results of
subsequent cache hits.)


-- glen


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