Compiler positions available for week ending September 13

This is a digest of ``help wanted'' and ``position available'' messages
received at comp.compilers during the preceding week. Messages must
advertise a position having something to do with compilers and must also
conform to the guidelines periodically posted in misc.jobs.offered.
Positions that remain open may be re-advertised once a month. To respond
to a job offer, send mail to the author of the message. To submit a
message, mail it to compilers@iecc.com.


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Subject: HDL (Verilog, VHDL, SystemVerilog) Compiler position at Xilinx (San Jose CA)
Date: Tue, 8 Sep 2009 12:41:03 -0700
From: Kumar Deepak <Kumar.Deepak@xilinx.com>


Hello all,


I manage a team in Xilinx that develops VHDL/Verilog/SystemVerilog logic
simulator called "ISim". I have a compiler position
<https://xapps9.xilinx.com/irec_prod/OA_HTML/OA.jsp?akRegionCode=IRC_VIS
_VAC_DISPLAY_PAGE&akRegionApplicationId=800&OASF=IRC_VIS_VAC_DISPLAY&OAH
P=IRC_EXT_SITE_VISITOR_APPL&transactionid=92529816&retainAM=N&addBreadCr
umb=RP&p_svid=36528&p_spid=1625008&oapc=5> open in my team. This
position is for San Jose, CA, USA.


I am looking for a compiler back-end expert who can help transition the
ISim's compilers from being basic (the current state) to being an
advanced optimizing one. The ISim compiler currently uses GCC after
converting ISim compiler's Intermediate Code Representation to assembly
like C to get executable code. We want to be able to write out more
optimal object code and generate object code directly (for Intel 32/64
bit architectures) without needing GCC to speed up compilation process
and to speed up simulation (by doing a better job of targeting the code
on combination of Intel/AMD processors and ISim simulation kernel).


If you are interested in exploring this position, please send your
resume to kumar@xilinx.com .


Thank you!
Kumar

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