|About exploring TLS parallelism email@example.com (2009-03-25)|
|Re: About exploring TLS parallelism firstname.lastname@example.org (Mayan Moudgill) (2009-03-27)|
|Re: About exploring TLS parallelism email@example.com (2009-03-30)|
|Re: About exploring TLS parallelism firstname.lastname@example.org (Mayan Moudgill) (2009-03-30)|
|Date:||Mon, 30 Mar 2009 07:44:26 -0700 (PDT)|
|Posted-Date:||30 Mar 2009 11:00:49 EDT|
On 3=D4=C227=C8=D5, =CF=C2=CE=E77=CA=B120=B7=D6, Mayan Moudgill <ma...@best=
> milla....@gmail.com wrote:
> > As mentioned in some papers, TLS ( Thread-level speculative)
> > parallelism is an important complementarity to the ILP. ...
> Further, the work to spawn and join threads, even with hardware
> assistance, is high enough that one really wants to be creating
> medium-sized threads. For the hardware mechanisms we looked at, we
> needed at least 50-100 instructions. So, a compiler will have to
> look globally to identify opportunities to kick off new threads. And
> that's hard - the alias/memory-carried dependence analysis in
> particular. There turns out not to be much difference between thread
> extraction and optimizations to identify task level
> parallelism. This may change if it becomes cheaper ...
> My suggestion (if this for a thesis) is to leave the compiler side
> alone, and concentrate on the hardware. At least there, the problems are
> tractable.- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 -
> - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 -
There're many hardware implementations to explore speculative thread-
level parallelism. Concentrating on the hardware may be a better way
,but the problem exists for that my advisor cannot afford the research
facility , that is, we have no environment to support us to do
research on the hardware mechanism of TLS. I'm imagining about such a
hardware simulation tool that could provide the following feature: It
support that one can add a hardware component designed by himself to
implement a mechanism in exploring the speculative thread-level
parallelism, and the simulator will adapt to the newly designed
hardware architecture and execute the program and give results after
I don't know many about the hardware simulators, and couldn't get a
clear view to decide which one could be the candidate. Could anyone
give some advice on it or just put forward criticism on my idea about
the simulation tool?
And also another issue, If I want to study the TLS based on some
compiler infrastructures, which would be a good choice? Open64?
Thanks very much!
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