Re: conditional based transfer patterns in md file

abhishekRoy <abhi353@gmail.com> writes:


> While updating the machine description file for our architecture ,we
> encountered the problem regarding conditional based transfer.
> In gcc internals specified that conditional based transfer can be
> supported using the standard pattern 'movModecc' as shown below.
> op0=(cc)? op2:op3
> But our architecture supports conditional transfer instruction as
> shown below:
> T<CC> op1, op2 It transfers the op1 to op2 if the <CC>
> is true otherwise it should behave like 'nop' .
> would u people tell me ,how to define the pattern in machine
> description file regarding the above specified issue.


You setup the conditional move, using a constraint of 0 in operand 1
to indicate it should be the same register as the destination. If the
register allocator had op2 and op3 in separate registers from the op0
register, it would insert a move of op2 to op0, and then do the insn.


Here is the cmov instruction from the i386 port. Note, it has two
alternatives, one to move when the condition is true, and one for when it is
false.


(define_insn "*movsicc_noc"
    [(set (match_operand:SI 0 "register_operand" "=r,r")
(if_then_else:SI (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(match_operand:SI 2 "nonimmediate_operand" "rm,0")
(match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
    "TARGET_CMOVE
      && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
    "@
      cmov%O2%C1\t{%2, %0|%0, %2}
      cmov%O2%c1\t{%3, %0|%0, %3}"
    [(set_attr "type" "icmov")
      (set_attr "mode" "SI")])




--
Michael Meissner
email: compilers@the-meissners.org
http://www.the-meissners.org

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