|Profile-driven optimization email@example.com (Tim Frink) (2008-01-29)|
|Re: Profile-driven optimization firstname.lastname@example.org (Gene) (2008-01-31)|
|Re: Profile-driven optimization email@example.com (=?ISO-8859-1?Q?Pertti_Kellom=E4ki?=) (2008-02-01)|
|Re: Profile-driven optimization firstname.lastname@example.org (M Wolfe) (2008-02-02)|
|Re: Profile-driven optimization email@example.com (Pasi Ojala) (2008-02-08)|
|Date:||Fri, 01 Feb 2008 13:14:26 +0200|
|Posted-Date:||01 Feb 2008 20:48:56 EST|
Tim Frink wrote:
> Based on that, they get one path through
> the program that is executed most frequently.
> I'm now wondering what sort of optimizations can be performed to that
A single instruction of a VLIW machine consists of a (fixed) number
of operations that the machine can execute in parallel. The operations
must be independent, i.e. one operation cannot use the output of
another as an input in the same cycle. This means that a VLIW machine
is potentially capable of impressive amounts of instruction level
parallelism, but only if the compiler is able to find it.
Typical basic blocks are relatively short, which limits the practical
amount of instruction level parallelism that the compiler can exploit.
So the trick that e.g. the Multiflow compiler used is to guess based
on the profiling information which basic blocks will usually be
executed in sequence, and do instruction scheduling (ordering of
instructions) on this larger region. Look up trace scheduling,
superblocks and hyperblocks for more information.
Since the IA-64 architecture can be thought of as VLIW-on-demand,
I suppose this is quite relevant there as well.
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