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| [8 earlier articles] |
| Re: Pitfalls in interference graph ? jeremy.wright@microfocus.com (Jeremy Wright) (2007-10-02) |
| Re: Pitfalls in interference graph ? shafitvm@gmail.com (shafi) (2007-10-15) |
| Re: Pitfalls in interference graph ? torbenm@app-6.diku.dk (2007-10-17) |
| Re: Pitfalls in interference graph ? SidTouati@inria.fr (ST) (2007-10-18) |
| Re: Pitfalls in interference graph ? rayiner@gmail.com (Rayiner Hashem) (2007-10-21) |
| Re: Pitfalls in interference graph ? Sid.Touati@uvsq.fr (Sid Touati) (2007-10-24) |
| Re: Pitfalls in interference graph ? parthaspanda22@gmail.com (2007-10-24) |
| From: | parthaspanda22@gmail.com |
| Newsgroups: | comp.compilers |
| Date: | Wed, 24 Oct 2007 11:26:17 -0700 |
| Organization: | Compilers Central |
| References: | 07-09-104 |
| Keywords: | registers |
| Posted-Date: | 24 Oct 2007 17:16:22 EDT |
> >I am trying to implement Briggs Optimistic register>allocator after
> >reading the the thesis written by Preston Briggs.
At optimization level 0, you may want not to
iterate like Briggs' or Chaitin's algorithm would.
Typically, a production compiler uses a quick
and dirty register allocator that uses coloring
and an interference graph, but it doesnt iterate.
> >Now for building the interference graph what other>than register pairs
> >is there any other issues that one has to look out> for?
Have you considered the case when virtual registers
are live upon entry to an exception handler?
Sincerely.
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