Call for papers: RAAW 2006 (Orlando, Dec 06)

Reconfigurable and Adaptive Architecture Workshop (RAAW)
To be held in conjunction with the
The 39th Annual IEEE/ACM International Symposium on Microarchitecture,
2006
Orlando, Florida
December , 2006


http://www.ws.binghamton.edu/raaw


Workshop Theme:


The tremendous advances in process technology provide architects and
microarchitects with many interesting opportunities for making use of
the huge transistor budget to enhance performance and increase
throughput. However, the complexity of software applications and system
software presents a challenging problem. The varying requirements of
the different applications running on a single machine, as well as the
changing behavior of a single application during its lifetime, make
choosing a suitable general purpose architecture a big challenge. This
raises the need for an architecture that can adapt to the different
requirements of the applications. The power consumption limits and the
growing importance of reliability further add to the appeal of such
adaptive architectures. Adaptive and reconfigurable architectures are
also becoming important in the embedded systems area. The
functionalities and the performance requirements of embedded systems
are increasing. However, the very low energy consumption requirements
of such systems have to be maintained.


The Reconfigurable and Adaptive Architecture Workshop provides a
high-quality forum for computer scientists and engineers to present
their latest research findings in the rapidly evolving field of
reconfigurable and adaptive architectures.




Submission Topics


Topics of interest include, but are not limited to:


        * High performance adaptive and reconfigurable architectures
        * Power-Aware and Thermal-Aware architectures
        * Adaptive architectures for enhanced hardware reliability
        * Compilation techniques for adaptive and reconfigurable
architectures
        * Dynamic compilation and runtime execution environments
        * Heterogeneous multiprocessing on a chip
        * Reconfigurable interconnection
        * Hardware/software trade-offs
        * Novel architectures and micro-architectures
        * Reconfigurable embedded computing systems
        * Memory management techniques
        * Profiling, measurement, and analysis techniques
        * Program phase detection techniques
        * Hardware acceleration through reconfiguration
        * FPGA-based systems


Submission Guidelines:


The Program Committee invites authors to submit papers up to 5000 words
in length, describing original, unpublished recent work related to the
workshop theme. Submission must be in pdf format and emailed to
raaw@binghamton.edu. The submission should include the contact person's
email address on the front page.


Extended version of some selected papers, included in the workshop
digest, will be published in Journal of Instruction-Level-Parallelism
(JILP)


At least one of the author(s) of an accepted paper is expected to
register for the workshop and present the paper.


Important Deadlines:


Paper Submission: September 8, 2006.


Acceptance Notification: October 13, 2006.


Final version of papers: October 27, 2006.


Organizers:


Aneesh Aggarwal
Electrical and Computer Engineering
SUNY Binghamton


Pradip Bose
IBM T. J. Watson Research Center


Mohamed Zahran
Electrical Engineering
City University of New York




Questions should be directed to the workshop co-organizers at
raaw@binghamton.edu


Program Committee:


David Albonesi (Cornell)
Doug Burger (UT Austin)
Alper Buyuktosunoglu (IBM)
Babak Falsafi (CMU)
Paolo Faraboschi (HP)
Krisztian Flautner (ARM)
Manoj Franklin (UMD)
Kanad Ghose (SUNY Binghamton)
Rajiv Gupta (Arizona)
Sudhanvu Gurumurthi (UVa)
Mary Hall (ISI)
Scott Mahlke (UMich)
Shubu Mukherjee (Intel)
John Paul Shen (Intel)
Marie Lou Soffa (UVa)
Stamatis Vassiliadis (TU Delft)

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