Re: VHDL Simulator

glen herrmannsfeldt <gah@ugcs.caltech.edu>
6 Feb 2006 00:07:14 -0500

          From comp.compilers
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VHDL Simulator t_somu@sasken.com (Soma Sekhar) (2006-02-02)
Re: VHDL Simulator nkavv@skiathos.physics.auth.gr (Uncle Noah) (2006-02-03)
Re: VHDL Simulator john_doef@yahoo.com (john Doef) (2006-02-03)
Re: VHDL Simulator mayank.ahuja@gmail.com (Mayank) (2006-02-03)
Re: VHDL Simulator gah@ugcs.caltech.edu (glen herrmannsfeldt) (2006-02-06)
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From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Newsgroups: comp.compilers
Date: 6 Feb 2006 00:07:14 -0500
Organization: Compilers Central
References: 06-02-011 06-02-032
Keywords: VHDL
Posted-Date: 06 Feb 2006 00:07:14 EST

Mayank wrote:


> Few VHDL simulators: Cadence's NC-Sim, Mentor's Modelsim and ghdl (GNU
> project). Google shall help you out, in case you need more details.


> I personally prefer NC-Sim because of capacity and performance reasons.


> Soma Sekhar wrote:


>>If anyone is doing projects on VHDL, please help me,
>>How to simulate VHDL codes, and what is the tool used ??


Also, Altera and Xilinx supply free tools to use to design logic
for their chips. These include a simulator.


-- glen


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