compiler design of network processor
2 Jul 2005 20:24:31 -0400

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compiler design of network processor (2005-07-02)
Re: compiler design of network processor find@my.address.elsewhere (Matthias Blume) (2005-07-03)
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Newsgroups: comp.compilers
Date: 2 Jul 2005 20:24:31 -0400
Organization: Bentium Ltd. (CN99)
Keywords: design, question
Posted-Date: 02 Jul 2005 20:24:31 EDT

    recently,I'm thinking on how to design a language which can fit the
network processor's features. the major blocks of Intel IXP network
processor shows below:
    1.Intel XScale core. General-purpose 32-bit RISC processor
compatible to ARM Version 5 Architecture. The Intel XScale core is
used to initialize and manage the
chip, and can be used for higher layer network processing tasks.
    2.Microengines (MEs). 8 32-bit programmable engines specialized for
network processing. Microengines do the main data plane processing per
    3.DRAM Controller. 1 DDR SDRAM controller. Typically DRAM is used
for data buffer storage.
    4.SRAM Controller. 2 independent controllers for QDR SRAM. Typically
SRAM is used for control information storage.
    5.Scratchpad Memory. 16 Kbytes of storage for general-purpose use.
    6.Media and Switch Fabric Interface (MSF) — Interface for network
framers and/or Switch Fabric. Contains receive and transmit buffers.
    7.Hash Unit. Polynomial hash accelerator. The Intel XScale core and
Microengines can use it to offload hash calculations.
    8.PCI Controller. 64-bit PCI Rev 2.2 compliant IO bus. PCI can be
used to either connect to a Host processor, or to attach PCI-compliant
peripheral devices.
    9.CAP. Chip-wide Control and status registers. These provide special
inter-processor communication features to allow flexible and efficient
inter-Microengine and Microengine-to-Intel-XScale-core communication.
    10.Intel XScale? Core Peripherals (XPI). Interrupt Controller,
Timers, UART,General-Purpose IO (GPIO) and interface to low-speed off
chip peripherals (such as maintenance port of network devices) and
Flash memory.
    11.Performance Monitor. Counters that can be programmed to count
selected internal chip hardware events; can be used to analyze and
tune performance.

    Currently, programs in network processor mainly writted in
assembler-like code,for Intel IXP network processor,they called the
microcode. when writting the microcode, programmer must use the
variables and registers explicitly. for example, when you declare a
variable, you must declare which type of memory or register you want
to put it in. It have too much complexity for developping application
on it.
    so, I think belows should be the basic principle of the language:
    1.only aimed at network packet processing.In this way, the developer
can focus on the application ,not on hardware details. I think it's
very useful for fast application development.
    2.portable for different network processor architecture. now many
network processor architecture exist, so I think the language can
abstract the hardware characteristics, and can port on different
hardware platform.
    3.hide for parallelism and synchronization,for network
processor,It's contain many parallel and synchronized operation. I
want to provide the user the feeling like the language is serial
operations,and we provide the techniques to switch from the serial
programm to the parrallel processing.
    upper is just a very simple consideration, and I'm looking for good
ideas,projects,references, papers and all what can help me to finish

frank zhang.

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