Related articles |
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[14 earlier articles] |
Re: Register allocation anton@mips.complang.tuwien.ac.at (2004-08-10) |
Re: Register allocation anton@mips.complang.tuwien.ac.at (2004-08-10) |
Re: Register allocation kym@kymhorsell.com (2004-08-11) |
Re: Register allocation kamalp@acm.org (2004-08-13) |
Register allocation thibault.langlois@di.fc.ul.pt (thibault.langlois@di.fc.ul.pt) (2005-05-13) |
Re: Register allocation rgd00@doc.ic.ac.uk (Rob Dimond) (2005-05-16) |
Re: Register allocation torbenm@diku.dk (2005-05-18) |
Re: Register allocation thibault.langlois@di.fc.ul.pt (thibault.langlois@di.fc.ul.pt) (2005-05-20) |
Re: Register allocation c3riechers@adelphia.com (Chuck Riechers) (2005-05-21) |
register allocation camille@bluegrass.net (David Lindauer) (2005-11-12) |
register allocation dgb@cs.washington.edu (1989-11-22) |
Re: register allocation larus@primost.wisc.EDU (1989-11-24) |
Register Allocation napi@rangkom.MY (1990-02-17) |
[8 later articles] |
From: | torbenm@diku.dk (=?iso-8859-1?q?Torben_=C6gidius_Mogensen?=) |
Newsgroups: | comp.compilers |
Date: | 18 May 2005 00:51:13 -0400 |
Organization: | Department of Computer Science, University of Copenhagen |
References: | 05-05-062 |
Keywords: | registers, optimize |
Posted-Date: | 18 May 2005 00:51:13 EDT |
"thibault.langlois@di.fc.ul.pt" <thibault.langlois@di.fc.ul.pt> writes:
> I have a question about register allocation using a graph coloring
> algorithm.
> The front-end of my compiler produces a three address code
> representation.
> The register allocation should be performed on the intermediate
> representation (to assign temporaries to registers) or should I choose
> the instructions of the target processor first, assuming an infinite
> number of registers and then use the register allocation to match the
> actual set of registers ?
There are advantages and disadvantages to both approaches:
If you do register allocation on intermediate code:
- You can share the register allocator among all target
architectures, just parameterising with number of registers etc.
- You can generate spill code as intermediate code, which the
instruction selector may optimise.
- The register allocator wil be simpler, as intermediate code is more
regular than machine code.
- But you will have to leve a few register unallocated, as the code
generator may have to use extra registers as temporaries etc.
With allocation on machine code:
- You can more easily handle instructions that require
operands/results in specific registers.
- You can tune the allocator better to the calling convention, i.e.,
regarding caller-saves/callee-saves registers, parameter registers
and spill.
- But spill code may break the optimality of instruction selection
and scheduling.
- And it is more work to port the register allocator to a different
target architecture.
Overall, I would say you get the best result by postponing register
allocation to machine code, but it will also be more work to do so.
Torben
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