Re: 96-bit integer modulo, Athlon64 gcc 64-bit integers, libc codefor 64-bit division, etc.

anton@mips.complang.tuwien.ac.at (Anton Ertl)
16 May 2005 11:16:56 -0400

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Related articles
[3 earlier articles]
Re: 96-bit integer modulo, Athlon64 gcc 64-bit integers, libc codefor gah@ugcs.caltech.edu (glen herrmannsfeldt) (2005-05-14)
Re: 96-bit integer modulo, Athlon64 gcc 64-bit integers, libc codefor christian.bau@cbau.freeserve.co.uk (Christian Bau) (2005-05-14)
Re: 96-bit integer modulo, Athlon64 gcc 64-bit integers, libc codefor gah@ugcs.caltech.edu (glen herrmannsfeldt) (2005-05-15)
Re: 96-bit integer modulo, Athlon64 gcc 64-bit integers, libc codefor anton@mips.complang.tuwien.ac.at (2005-05-15)
Re: 96-bit integer modulo, Athlon64 gcc 64-bit integers, libc codefor christian.bau@cbau.freeserve.co.uk (Christian Bau) (2005-05-15)
Re: 96-bit integer modulo, Athlon64 gcc 64-bit integers, libc codefor gah@ugcs.caltech.edu (glen herrmannsfeldt) (2005-05-15)
Re: 96-bit integer modulo, Athlon64 gcc 64-bit integers, libc codefor anton@mips.complang.tuwien.ac.at (2005-05-16)
Re: 96-bit integer modulo, Athlon64 gcc 64-bit integers, libc codefor Jonathan_Epstein@nih.gov (Jonathan Epstein) (2005-05-16)
Re: 96-bit integer modulo, Athlon64 gcc 64-bit integers, libc codefor Jonathan_Epstein@nih.gov (Jonathan Epstein) (2005-05-20)
| List of all articles for this month |

From: anton@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.compilers
Date: 16 May 2005 11:16:56 -0400
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
References: 05-05-063 05-05-082 05-05-098 05-05-108 05-05-116 05-05-129
Keywords: performance

glen herrmannsfeldt <gah@ugcs.caltech.edu> writes:
>Christian Bau wrote:
>
>> glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote:
>
>(snip)
>
>>>Does the OS save the full 64 bit registers when not in 64 bit mode?
>
>(snip)
>
>> or the designers are really really and I mean really
>> absolutely incredibly braindamaged stupid. I would assume the first.


The designers of what? Of gcc? MacOS X boxes are not the only PPCs
that gcc targets, so I find no fault there. Of MacOS X? They built
an OS for 32-bit CPUs that happens to run on a 64-bit CPU, so I find
no fault there, either.


>The case I was thinking of was running a 32 bit OS on a 64 bit
>architecture that is an extension of a 32 bit architecture.


An example I know of was the first Solarises on UltraSPARCs. In
theory one could use the 64-bit registers, but the 32-bit OS saved
only 32 bits on context switches. I am pretty sure the same is true
for Ultrix on the DecStation 5000/150 (with an R4000).


>Say, for example, Win2000 on AMD-64 (x86-64).


Bad example, because the x86-64 architecture is not an extension of
the 386 architecture in that sense, i.e., you cannot use 64-bit
instructions in legacy or compatibility mode (W2K runs in legacy
mode), and you cannot use 386 code in 64-bit mode. The x86-64
architecture supports 3 different instruction sets: 8086, 386 32-bit
mode instructions plus extensions, and x86-64 long mode instructions;
there are a bunch of modes and submodes that determine which
instruction set is currently being executed.


In contrast, PPC64 is an extension of PPC32 (actually, the
documentation says that PPC32 is a subset of PPC64) and MIPS-IV is an
extension of MIPS; you can run 32-bit and 64-bit code in the same
mode. IIRC this is mostly true for SPARC, but they did add some mode
bit because of register windows.


- anton
--
M. Anton Ertl
anton@mips.complang.tuwien.ac.at
http://www.complang.tuwien.ac.at/anton/home.html
[Thanks, but I think we've left compiler-land now. -John]



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