Re: Operation Latencies

12 Feb 2004 11:02:16 -0500

          From comp.compilers

Related articles
Operation Latencies (2004-02-08)
Re: Operation Latencies (TOUATI Sid) (2004-02-12)
Re: Operation Latencies (2004-02-12)
Re: Operation Latencies (Tommy Hoffner) (2004-02-13)
| List of all articles for this month |

From: TOUATI Sid <>
Newsgroups: comp.compilers
Date: 12 Feb 2004 11:02:16 -0500
Organization: Universite de Versailles Saint-Quentin-en-Yvelines
References: 04-02-090
Keywords: optimize, architecture
Posted-Date: 12 Feb 2004 11:02:16 EST

Memory access latencies are unknown at compile time. Compilers have two
1- being optimistic : assume the data in cache. So the latency is a
cache access. This is the most usual action that compilers do;
2- being pessemistic : assume data in memory. Huge static latencies
would suffer the register allocator and ILP scheduler.

There is some research papers that try to classify memory accesses
depending if they would be assumed as cache hits or misses. Meanwhile,
you can never assert at compile time if this data would be in the cache
or not (many dynamic phenomenas arise, interactions with OS, etc). All
what you can do is to hope that what you guessed at compile time would
happen at execution time

Post a followup to this message

Return to the comp.compilers page.
Search the comp.compilers archives again.