Compiler positions available for week ending September 21

This is a digest of ``help wanted'' and ``position available'' messages
received at comp.compilers during the preceding week. Messages must
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conform to the guidelines periodically posted in misc.jobs.offered.
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From: Human Resources <hr@tharas.com>
Date: Fri, 19 Sep 2003 10:37:49 -0700 (PDT)
Subject: Compiler Optimization/Parallel Processing Position, Santa Clara, CA




We are looking for a innovative problem solver with experience in
developing compiler optimizations and program transformations. You
will apply these techniques to a parallel hardware description
language (Verilog/VHDL) Compiler that targets a special purpose VLIW
architecture for simulation.


Requirements:


o MS CS or equivalent with 6+ years or PhD with 0-2 years


o Experience in multi-person, large software project teams


o Software Development experience in a Unix/C++ Environment


o Experience in developing Graph Algorithms


o Experience in developing Code Optimization Phases


o Dataflow Analysis


Preferred Experience:


o Loop Restructing/Optimization


o Knowledge of HDL Semantics and Simulation Algorithms


o Partitioning/Scheduling of Parallel Programs


Job Location: Santa Clara, California, USA


Submit your resumes in plain text to: hr@tharas.com


http://www.tharas.com


Tharas Systems Inc., 3016 Coronado Drive, Santa Clara, CA 95054

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