Re: q: gcc backend condition codes

Chris Dollin <kers@hplb.hpl.hp.com>
22 Jun 2003 23:21:13 -0400

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Related articles
q: gcc backend condition codes erez@savan.com (Erez Doron) (2003-06-20)
Re: q: gcc backend condition codes kers@hplb.hpl.hp.com (Chris Dollin) (2003-06-22)
Re: q: gcc backend condition codes jle@forest.owlnet.rice.edu (2003-06-25)
Re: q: gcc backend condition codes mrmnews@the-meissners.org (Michael Meissner) (2003-07-02)
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From: Chris Dollin <kers@hplb.hpl.hp.com>
Newsgroups: comp.compilers
Date: 22 Jun 2003 23:21:13 -0400
Organization: HPLB
References: 03-06-092
Keywords: GCC, architecture
Posted-Date: 22 Jun 2003 23:21:13 EDT

Erez Doron wrote:


> I'm trying to port gcc to a new processor.
> the assembeler does not have a flags register.
> instead, every instruction can be preceded with a condition.
>
> e.g.
> if r1>r2 mov r2,r1
>
> is a maximum function.


I don't know how to do it, but the ARM is like that, and isn't there
an ARM back-end for GCC already? So you could steal\\\\\re-use
whatever tactics they did.


--
Chris "very fond of the ARM instruction set" Dollin
C FAQs at: http://www.faqs.org/faqs/by-newsgroup/comp/comp.lang.c.html
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