Re: Machine descriptions for code generation?

"Rainer Leupers" <leupers@iss.rwth-aachen.de>
18 Oct 2002 23:21:39 -0400

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Machine descriptions for code generation? eml.riverside-machines.com@eu.uu.net (Evan Lavelle at dot) (2002-10-13)
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From: "Rainer Leupers" <leupers@iss.rwth-aachen.de>
Newsgroups: comp.compilers
Date: 18 Oct 2002 23:21:39 -0400
Organization: RWTH Aachen
References: 02-10-035
Keywords: code, architecture
Posted-Date: 18 Oct 2002 23:21:39 EDT

Our ISS institute has built a tool suite around the LISA processor
modeling language, which eliminates the model consistency problems you
mention.


It allows automatic generation of software tools (simulator, debugger,
profiler, assembler, linker) and HDL synthesis models (RTL) from a
single LISA processor specification. In addition, it supports


SoC integration and mutiprocessor debugging. We are also working on
automatic generation of C compilers from LISA models. The other tools
are already operational and have been productized by LISATek
Inc. Please have a look at http://www.lisatek.com for more
information.


Rainer
--
Prof. Dr. Rainer Leupers
Aachen University of Technology
Integrated Signal Processing Systems
SSS - 611920, Templergraben 55, 52056 Aachen, Germany
ph: +49 241 80-28301, fax: -28306, mobile: +49 177 2131146
email: leupers@iss.rwth-aachen.de
WWW: http://www.iss.rwth-aachen.de

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