Compiler positions available for week ending May 19

This is a digest of ``help wanted'' and ``position available'' messages
received at comp.compilers during the preceding week. Messages must
advertise a position having something to do with compilers and must also
conform to the guidelines periodically posted in misc.jobs.offered.
Positions that remain open may be re-advertised once a month. To respond
to a job offer, send mail to the author of the message. To submit a
message, mail it to compilers@iecc.com.




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From: jxue@cse.unsw.edu.au (Jingling Xue)
Date: Fri, 17 May 2002 15:38:41 +1000
Subject: Senior Research Associate, Australia


We are looking for someone to work on an exciting project in
the area of programming languages, compilers & operating systems
in the School of Computer Science and Engineering at UNSW.


The job description is available from:


http://www.hr.unsw.edu.au/employment/26040207.htm


The project details can be found from:


http://www.cse.unsw.edu.au/~chak/project/sec/


  Jingling Xue
| Tel: +61 2 9385 4889 School of Computer Science and Engineering |
| Fax: +61 2 9385 5995 The University of New South Wales |
| http://www.cse.unsw.edu.au/~jxue Sydney 2052 Australia |




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From: "Dr. Andy Nisbet" <Andy.Nisbet@cs.tcd.ie>
Subject: Compiler & FPGA Postgraduate Vacancies at Trinity College Dublin
Date: Wed, 22 May 2002 10:44:21 +0100
Organization: TCD, Ireland (post does not reflect views of Trinity College)


Hello,
there are currently 4 positions in compilation and FPGA applications to be
filled in the Department of Computer Science, Trinity College, Dublin. We
hope to fill the positions within the next couple of months.


For further details contact: Andy.Nisbet@cs.tcd.ie
Phone:00353-(0)1-608-3682
Fax: 00353-(0)1-677-2204


IDEAS: Iterative Design Tools for Embedded FPGA Systems


Reference Number: IDEAS/IF2002/035


This project aims to deliver automatic and interactive tools for the
transformation of C programs into HandelC/SystemC specifications for
FPGA targets. The project will utilise the SUIF compiler
infrastructure for this research. The project will develop an fpgapass
loop transformation driver and suif2handelc and suif2systemc compiler
backends for the SUIF infrastructure. This will enable the ability to
generate Handel-C and SystemC specifications from augmented SUIF
internal representations produced by fpgapass. Thus, it will be
possible to generate transformed Handel-C and SystemC specifications
from applications coded in C.




Under this TWO YEAR grant, there are 2 positions for candidates
having, or about to obtain M.Sc. level qualifications, or equivalent
work experience in Computer Science, Electronics or a strongly related
discipline. The ideal applicants would have knowledge/experience of
SUIF-1/SUIF-2 and possibly experience of programming FPGAs using
HandelC/SystemC. Other relevent skills would include C++ and UNIX.


Salary (Normally Tax free if registered for higher degree):
Year 1 circa Euro 16K
Year 2 circa Euro 19K


====
Hardware Acceleration of High Performance Computing Applications


Reference Number: SC/02/288


Computationally demanding high performance computing applications
achieve performance by restructuring their communication/data access
patterns in order to efficiently match target machine
characteristics. In this project we seek to investigate the reverse of
this process where performance is achieved by reconfiguring hardware
to match application characteristics. The project aims to demonstrate
that reconfigurable computing hardware based on Field Programmable
Gate Array (FPGA) technology can provide a cost effective platform for
the accelerated execution of high performance computing applications.
The project will implement and optimise FPGA accelerated versions of a
lattice quantum chromodynamics (QCD) and an image segmentation
application. Floating-point arithmetic will be replaced by a
logarithmic arithmetic unit developed under the ESPRIT High Speed
Logarithmic Arithmetic Long Term Research Project 33544.


Under this THREE YEAR grant, there are 2 positions for candidates
having B.Sc. level qualifications in Computer Science, Electronics,
Mathematics, Physics or a strongly related discipline. The ideal
candidates would have experience of programming FPGAs using HandelC,
or of high performance computing applications.


Salary (Normally Tax free if registered for higher degree):
Year 1 circa Euro 12k
Year 2 circa Euro 14k
Year 3 circa Euro 16K


Cheers,
                        Andy


Dr. Andy Nisbet, ORI.LG.19, Dept. of Computer Science,
                            Trinity College, Dublin 2, Ireland
                            Email: Andy.Nisbet@cs.tcd.ie
Phone: +353-(01)-608-3682 FAX: +353-(01)-677-2204




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Date: Wed, 22 May 2002 18:35:04 -0700
From: Ramesh Narayanaswamy <ramesh@tharas.com>
Reply-To: hr@tharas.com
Subject: Compiler Position, Santa Clara, CA


Software Engineer - Compilers


We are looking for a innovative problem solver with experience in
developing compiler optimizations and program transformations. You
will apply these techniques to a parallel hardware description
language (Verilog) Compiler that targets a special purpose VLIW
architecture for simulation.


Requirements:


o MS CS or equivalent with 6+ years of experience in large multi
                person software projects


o Software Development experience in a Unix/C++ environment


o Experience in developing graph algorithms


o Experience in developing code optimization phases


o Dataflow Analysis


Preferred Experience:


o Loop Optimization


o Knowledge of HDL Semantics and Simulation Algorithms


o Scheduling Algorithms


Job Location: Santa Clara, California, USA


Submit your resumes in plain text to: hr@tharas.com


http://www.tharas.com


Tharas Systems Inc., 3016 Coronado Drive, Santa Clara, CA 95054


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From: "Sridhar" <sridhardoss@vsnl.com>
Subject: Fw: Compiler positions in HCL CISCO in Chennai-India
Date: Thu, 23 May 2002 10:37:31 +0530


Compiler positions in HCL CISCO in Chennai-India




Technical skills required


Experience with Developing lexical
Analyses,parsers,code generators.
Experience with developing /Maintaining code optimization algorithms,passes
of compilers
Experience with assembly level optimization techniques,register coboring,
Peep hole optimization
Experience with Motorola , SPARC,RISC,Power PC, Processors .
Experience with Solaris Development Environment




Sridhar Doss
Niche Consulting

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