Re: Hardware Bounds Checking

Pramod Ramarao <pramod@linux-1.ee.iastate.edu> wrote:
>Hello everyone,
>Sometime back, there was a lengthy discussion about this topic on
>comp.compilers. One of the guys mentioned about the Unisys A-series
>mainframe capable of performing bounds checking in hardware using a
>structure called Actual Segment Descriptor(ASD). ASD contains the base
>address, length and type of the array.


I haven't heard the term, but believe I know the concept.


>I was wondering as to how the ASDs are actually filled with the
>corresponding data? Doing so with the compiler(obviously) would lead to a
>performance degradation but they claim a low performance overhead. Am I
>missing something?


Yes :-) In suitable languages (which include Algol 68 and Fortran, but
not C), and their usual coding paradigms, the overhead of managing the
descriptors is small. In fact, it can even be negative, by reducing
the need for size parameters to be passed separately.


The point is that array element references are vastly more common than
either the passing of array parameters or the slicing of arrays into
subarrays. Both of the latter need extra work, but the former
doesn't. Given the wasted cycles on modern CPUs, array bound checking
could be provided for free.


>Also, could a vairant of this scheme also be adopted to present
>superscalar processors with low overhead?


It applies to pretty well any architecture. There ARE architectures
that it couldn't be made efficient on, but they are pretty bizarre.


The real point is that it doesn't apply well to languages like C,
where arrays and pointers are interchangeable and the relevant upper
bound varies with context even within a single expression. This
causes havoc with optimisation, anyway.


Regards,
Nick Maclaren,
University of Cambridge Computing Service,
New Museums Site, Pembroke Street, Cambridge CB2 3QH, England.
Email: nmm1@cam.ac.uk
Tel.: +44 1223 334761 Fax: +44 1223 334679

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