Re: rescheduling VLIW compilation

Gilles Pokam <Gilles.Pokam@irisa.fr>
24 Mar 2002 00:18:55 -0500

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Related articles
rescheduling VLIW compilation rramanar@ecs.umass.edu (Ramshankar Ram) (2002-03-09)
Re: rescheduling VLIW compilation Gilles.Pokam@irisa.fr (Gilles Pokam) (2002-03-17)
Re: rescheduling VLIW compilation Gilles.Pokam@irisa.fr (Gilles Pokam) (2002-03-24)
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From: Gilles Pokam <Gilles.Pokam@irisa.fr>
Newsgroups: comp.compilers
Date: 24 Mar 2002 00:18:55 -0500
Organization: IRISA, Campus de Beaulieu, 35042 Rennes Cedex, FRANCE
References: 02-03-029
Keywords: optimize, architecture
Posted-Date: 24 Mar 2002 00:18:55 EST

Ramshankar Ram wrote:


> I am looking to sequentialize a set of scheduled assembly statements
> with parallelism information.


I had also worked on a problem similar to yours. It was a code that was
scheduled for a 4-issue VLIW machine. The first thing I made was to apply
register renaming. It was obvious for me because I had constructed the
SSA form from the CFG representation. Register renaming eliminates most
false dependencies inside or even across long instructions word. This
eases the sequentialization process once you have constructed the DAG.
You could also think of applying new scheduling algorithms and register
allocation techniques at the place.


Gilles
IRISA, CAPS Team
gilles.pokam@irisa.fr

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