Announcement: Verilog interpreter source available for non-commercial study (Steve Meyer)
28 Jan 2002 01:01:36 -0500

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Announcement: Verilog interpreter source available for non-commercia (2002-01-28)
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From: (Steve Meyer)
Newsgroups: comp.compilers
Date: 28 Jan 2002 01:01:36 -0500
Organization: Global Network Services - Remote Access Mail & News Services
Keywords: available, architecture
Posted-Date: 28 Jan 2002 01:01:36 EST

The Pragmatic C Verilog simulator is now being distributed in source
form and it is free for non-commercial use such as studying the details
of a commercial "real world" full IEEE P1364 Verilog interpreted
simulator, i.e. signals usually have 3 vector components allowing 128
different values and delays can be back annotated anytime during

A license must be purchased to redistribute Cver or to use it to design or
verify commercial electronics, but it is free for non-commercial use.
See web site for more details and for instructions
on obtaining Cver.

The Verilog hardware description language (HDL) is quite complex so there
are many interesting compiler algorithms in the program such as a very
complex hand crafted scanner (hardware designers are not big on token
definition or language regularity and end-of-file is just white space).
It uses operator precedence parsing for expressions using algorithm that
I remember (maybe wrongly) from Professor Gries' compiler class.

It uses commercial interpreter that is only 3 times or so slower than
compiled simulators for real hardware designs and is actually often
faster if interpreter type features such as PLI (programming language
interface) access is needed. I think it shows that the optimizations
for Verilog discussed in R. Allen's recent book are not very useful.

Steve Meyer Phone: (612) 371-2023
Pragmatic C Software Corp. email:
520 Marquette Ave. So., Suite 900
Minneapolis, MN 55402

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