Related articles |
---|
Indirect threading other than GCC? heng@ag.arizona.edu (Heng Yuan) (2001-12-08) |
Re: Indirect threading other than GCC? anton@mips.complang.tuwien.ac.at (2001-12-09) |
Re: Indirect threading other than GCC? nickgeo@merle.acns.nwu.edu (Nicholas Geovanis) (2001-12-11) |
Re: Indirect threading other than GCC? anton@mips.complang.tuwien.ac.at (2001-12-15) |
From: | Nicholas Geovanis <nickgeo@merle.acns.nwu.edu> |
Newsgroups: | comp.compilers |
Date: | 11 Dec 2001 21:36:15 -0500 |
Organization: | Northwestern University, Evanston, IL, US |
References: | 01-12-034 01-12-037 |
Keywords: | architecture, performance |
Posted-Date: | 11 Dec 2001 21:36:15 EST |
...Having looked at the threading-performance info on your
website a bit...
Tell me whether I understand the Pentium indirect-threading performance
penalty which you documented in 1995: An I-cache miss causes cache
invalidation for *both* I- and D-caches, which means that with a "normal"
(unoptimised) indirect-thread implementation each cache would be
invalidated, flushed and filled twice for *each and every* thread "jump".
Do I have that right? This was only on the original Pentium?
Thanks...Nick G, who once wrote an indirect-threaded Forth 79
interpreter for the IBM/370 running VM/CMS ;-)
* Nick Geovanis Ignorance and blind passions abound, pervading
| IT Computing Svcs everywhere like particles of dust.
| Northwestern Univ Desire and hatred arising out of conflict and
| n-geovanis@nwu.edu accord are like high peaks and ridges.
+-------------------> -- Shinran Shonin
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