EPIC-1 : 1st Workshop on Explicitly Parallel Instruction Computing Architectures and Compiler Technology

                                                                    EPIC-1


                                              CALL FOR PAPERS


              1st Annual Workshop on Explicitly Parallel Instruction
                    Computing Architectures and Compiler Technology


                              Held in conjunction with MICRO-34


                                            Austin, Texas, USA


                    SUBMISSION DEADLINE: September 28th, 2001
              (extended to October 5th)


The Explicitly Parallel Instruction Computing (EPIC) architecture
model has the potential of achieving unparalleled levels of
performance in future computer systems. The EPIC style of
architecture was developed to enable higher levels of
instruction-level parallelism. By allowing the compiler to express
program parallelism and other relevant information directly to the
processor, EPIC architectures can overcome hardware complexity issues
that limit performance in traditional microprocessors. The major
challenge to realizing the full potential of EPIC architectures is
developing strategic compiler technologies that effectively deploy
explicitly defined hardware mechanisms and deliver performance for
both commercial and scientific applications. This one-day workshop
will focus on promising research concepts that enable the EPIC
architecture model.




TOPICS OF INTEREST


* Topics of EPIC architectures and compiler technologies or related studies
    focusing on the following:
    - Predicated execution
    - Compiler-directed control speculation
    - Compiler scheduling and optimization techniques for instruction-level
        parallelism
    - EPIC performance monitoring unit feedback for dynamic compilation
    - Tools, compilers, and infrastructure for EPIC architectures
    - Data and value speculation
    - Hardware features to support instruction-level parallelism
    - Compiler controlled memory prefetching and memory hierarchy management
    - Support for software pipelining
    - Effects of architectural features on workload behavior
    - Novel architectures and micro-architectures
    - Experimental evaluation of Itanium microprocessors
    - Commercial and scientific workload studies for EPIC models
    - Power and energy aware computing techniques for EPIC machines
    - Performance analysis of EPIC architectures


IMPORTANT DATES
Submission Deadline: September 28, 2001 (extended to Oct 5th)
Acceptances Mailed: October 31, 2001
Final Version Due: November 23, 2001


Full papers of up to 20 pages or extended abstracts of approximately 8
pages can be submitted. Clearly describe the nature of the work, its
significance and the current status of the research. Include a title
page containing the title of the paper, list of authors and their
affiliations, addresses, telephone and fax numbers, email addresses
and the name of the corresponding author.


Please submit papers and extended abstracts to:


                  http://systems.cs.colorado.edu/EPIC1/


General Chair: Dan Connors University of Colorado
Program Chairs: Carole Dulong Intel Corporation
                                                              Rick Hank Hewlett Packard Corporation


PROGRAM COMMITTEE:


Santosh Abraham Sun Microsystems
David August Princeton University
Brad Calder University of California-San Diego
Dan Connors University of Colorado
Tom Conte North Carolina State University
Kemal Ebcioglu IBM Research
Wen-mei Hwu University of Illinois
Suneel Jain Hewlett-Packard Corporation
Teresa Johnson Hewlett-Packard Corporation
Vinod Kathail Hewlett-Packard Research Labs
Dan Lavery Intel Corporation
Scott Mahlke University of Michigan
Krishna Palem Georgia Tech University
Jim Pierce Intel Corporation
Nancy Warter Cal State-Los Angeles


For more information on EPIC-1:
                  http://systems.cs.colorado.edu/EPIC1/

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