Workshop on Binary Translation - 2001

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                                        Workshop on Binary Translation - 2001
                                                                WBT-2001


                        In Conjunction with the International Conference on
                Parallel Architectures and Compilation Techniques (PACT'2001)
                                      http://http://www.ac.upc.es/pact01
                Barcelona, Catalunya, Spain PACT'2001: September 8-12, 2001


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OBJECTIVE
---------


WBT-2001 seeks to continue the high level of interest in the first two
Workshops on Binary Translation held with PACT'99 and PACT'2000. There are
many academic and industrial projects on binary translation and WBT-2001
will provide a forum for researchers and practitioners to meet, thus
stimulating the exchange of ideas and experiences with binary translation,
and opening new avenues of research. WBT-2001 seeks submissions describing
novel ideas or experience with building binary translation systems. There
will be a limited number of talks in order to allow the audience to
participate.


IMPORTANT DATES
---------------
July 2, 2001 Papers Due
August 7, 2001 Notification of Acceptance
August 21, 2001 Final Papers Due
September 2001 Workshop


FORMAT AND SUBMISSION
---------------------
  o Electronic submissions only to: wbt@watson.ibm.com
  o 10 pages or less
  o In PDF or Level 1 or 2 PostScript
  o Viewable in Ghostview
  o Printable on USLetter (8.5 x 11 inch page) sized paper


Please include the following information in plain text with the submitted
paper: [1] Author Name(s), [2] Postal Address, [3] Phone Number, [4] FAX
Number, [5] Email Address, [6] Title of Paper, [7] 5 Keywords, and
[8] Abstract.


PROCEEDINGS
-----------
o Photocopied Proceedings will be distributed at the workshop


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TOPICS
------
-> Dynamic (Runtime) Translation
        o With operating system support
        o Without operating system support
        o Java
        o From traditional architectures such as Alpha, IA32, MIPS,
            PowerPC, and SPARC to new architectures


-> Static Translation
        o With no runtime assistance/translation
        o With runtime assistance/translation (Hybrid Translation)


-> General techniques and problems
        o Compatibility
              * Self-modifying code
              * Self-referential code
              * Precise exceptions
              * Other issues
        o Scheduling and optimization
        o Adapting code to changing program behavior
        o On-the-fly reconstruction of CFG's and data dependences
        o Management of translated code
        o Other compilation challenges


-> Hardware Support
        o Hardware Assists for Binary Translation
              * Interpretation Engines
              * Profiling Branch Directions, Instructions with Cache Misses, etc.
          o Hardware Mechanisms Employing Binary Translation Techniques
              * Pipeline cracking CISC operations into micro-ops, a la Pentium Pro
              * Cached hardware schedules a la DIF
              * Other Mechanisms


ORGANIZERS
----------
Erik Altman IBM T.J. Watson Research Center
David Kaeli Northeastern University


Program Committee
-----------------
Sanjeev Banerjia InCert
Cristina Cifuentes University of Queensland/Sun
Evelyn Duesterwald HP Cambridge Labs
Roger Espasa Universitat Politecnica de Catalunya
Shalom Goldenberg Intel Israel
Jose Gonzalez Universidad de Murcia
David Keppel Transmeta
Andreas Krall Technical University of Vienna
Bilha Mendelson IBM Israel
Soo-Mook Moon Seoul National University
Shubu Mukherjee Compaq
Ravi Nair IBM T.J. Watson Research Center
Markus Pilz University of Zurich
Michiel Ronsse Ghent University
Richard Schooler InCert
Amitabh Srivastava Microsoft Research
Youfeng Wu Intel

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