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| Related articles |
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| Compiler requirements...help needed neal.a.benedict@intel.com (Benedict, Neal A) (2000-11-01) |
| Re: Compiler requirements...help needed smoleski@surakware.com (Sebastian Moleski) (2000-11-04) |
| Re: Compiler requirements...help needed tnaran@direct.ca (Travers Naran) (2000-11-04) |
| Re: Compiler requirements...help needed rbenedik@fsmat.htu.tuwien.ac.at (Ronald Benedik) (2000-11-05) |
| Re: Compiler requirements...help needed clc5q@cs.virginia.edu (Clark L. Coleman) (2000-11-07) |
| From: | "Clark L. Coleman" <clc5q@cs.virginia.edu> |
| Newsgroups: | comp.compilers |
| Date: | 7 Nov 2000 13:06:12 -0500 |
| Organization: | University of Virginia |
| References: | 00-11-018 |
| Keywords: | design, practice |
Ronald Benedik wrote:
> The newer Intel Processors have Performance Monitor Counters
>implemented. So the user can use them in optimizing L2 cache accesses.
>However there's no such feature for the L1 cache. I think it would
>improve the compiler if it optimizes not only the register pressure,
>but also for the L1 cache. I think that would be managable
>because of the limited size of the L1 cache.
There have been L1 cache counters for as long as there have been
performance counters in the Intel processors, going back to the 60 MHz
Pentium. Check out Appendix A of the P6 Family System Programmer's
Guide, section A.1, from
ftp://download.intel.com/design/PentiumII/manuals/24319202.pdf
Look at counter 45H (hex value in counter select field.) This counter
is incremented every time a line is brought into the L1 D-cache.
Clark Coleman
University of Virginia
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