MICRO-33 Advance Program

The organizing committee is pleased to announce the 33rd International
Symposium on Microarchitecture (MICRO-33) to be held in Monterey,
California from Dec. 10 to Dec. 13, 2000. MICRO represents the premier
technical forum for discussing issues related to instruction-level
parallelism, compilation techniques, and microarchitectures. This
year's program is excellent (full program included below),
highlighted by:


        * 4 pre-symposium workshops
- Feedback-Directed and Dynamic Optimization
                - Multithreaded Execution, Architecture and Compilation
                - Media Processors and DSPs
                - Kool Chips
        * 1 post-symposium tutorial ***NEWLY ADDED***
                - Dynamic Binary Translation and Optimization
        * 3 keynote lectures
- "Breathing Life Into a Paper Tiger"
                - "Defect Tolerant Molecular Electronics: Algorithms,
                      Architectures, and Atoms"
                - "A Whole New Ballgame - Supercomputing on Two AA Batteries"
        * 31 high-quality technical papers


Monterey offers the history of an old fishing town as well as
spectacular views of the Pacific ocean. The conference hotel, the
Monterey Plaza Hotel, is a short walk from Fisherman's Wharf and the
Monterey Bay Aquarium. The hotel has agreed to hold a limited number
of rooms for conference attendees until November 9, 2000. The
advance-registration deadline is Nov. 15, 2000.


For further information see, http://www.microarch.org/micro33


Scott Mahlke
Micro-33 Publicity Chair
HP Laboratories, Palo Alto, CA
mahlke@hpl.hp.com




************************************************************
                                      Advance Program: MICRO-33
                    International Symposium on Microarchitecture
                                          December 10-13, 2000
                                            Monterey California


                                                    Sponsored by
                                  IEEE TC-MARCH And ACM SIGMICRO


                                              Corporate Sponsors:
                      S3, Hewlett-Packard, Intel, SGI, Compaq, IBM


General information is available at the official
MICRO-33 web-site at: http://www.microarch.org/micro33
************************************************************


Sunday Dec. 10, 2000


8:00-18:00 Workshops


    3rd ACM Workshop on Feedback-Directed and Dynamic Optimization
    Chairs: Susan Eggers (University of Washington), Michael Smith
    (Harvard University)


    2nd Workshop on Media Processors and DSPs
    Chairs: Bill Mangione-Smith (UCLA), David Baker (BOPS)


    Workshop on Multithreaded Execution, Architecture and Compilation
    Chairs: Walid Najjar (Colorado State University), Antonio Gonzalez
    (UPC Barcelona)


    Kool Chips Workshop
    Chairs: Dirk Grunwald (University of Colorado), Mary Jane Irwin
    (Penn. State University), Trevor Mudge (University of Michigan)


Monday Dec. 11, 2000


8:00-9:30 Welcome and First Keynote


    Breathing Life Into a Paper Tiger
    Darrell Boggs (Intel)


10:00-12:00 Memory Hierarchy
Session Chair: Ronny Ronen (Intel)


    Eager Writeback - A Technique for Improving Bandwidth Utilization
    Hsien-Hsin Lee, Gary Tyson (University of Michigan), Matthew Farrens
    (University of California, Davis)


    Silent Stores for Free
    Kevin M Lepak, Mikko H Lipasti (University of Wisconsin - Madison)


    A Permutation-based Page Interleaving Scheme to Reduce Row-buffer
    Conflicts and Exploit Data Locality
    Zhao Zhang, Zhichun Zhu , Xiaodong Zhang (College of William and
    Mary)


    Predictor-Directed Stream Buffers
    Timothy Sherwood, Suleyman Sair, Brad Calder (University of
    California, San Diego)


12:00-13:30 Lunch and Second Keynote


    Defect Tolerant Molecular Electronics: Algorithms, Architectures,
    and Atoms
    Phil Kuekes (Hewlett-Packard)


13:30-15:30 Superscalar Architecture
Session Chair: Gary Tyson (University of Michigan)


    On Pipelining Dynamic Instruction Scheduling Logic
    Jared Stark (Intel), Mary D Brown, Yale N Patt (University of
    Texas at Austin)


    The Impact of Delay on the Design of Branch Predictors
    Daniel A Jimenez, Stephen W Keckler, Calvin Lin (University of
    Texas at Austin)


    Improving BTB Performance in the Presence of DLLs
    Stevan A Vlaovic, Edward S Davidson, Gary S Tyson (University of
    Michigan)


    Efficient Checker Processor Design
    Saugata Chatterjee, Christopher Weaver, Todd Austin (University of
    Michigan)


16:00-17:30 Compilation
Session Chair: Carol Thompson (Hewlett-Packard)


    An Integrated Approach to Accelerate Data and Predicate
    Computations in Hyperblocks
    Alexandre Eichenberger (North Carolina State University), Waleed
    Meleis, Suman Maradani (Northeastern University)


    Accurate and Efficient Predicate Analysis with Binary Decision
    Diagrams
    John W Sias, Wen-mei W Hwu (University of Illinois at Urbana-
    Champaign), David I August (Princeton University)


    Modulo Scheduling for a Fully-Distributed Clustered VLIW
    Architecture
    Jesus Sanchez, Antonio Gonzalez (Universitat Politècnica de
    Catalunya)


Tuesday Dec. 12, 2000
8:30-9:30 Third Keynote


    A Whole New Ballgame - Supercomputing on Two AA Batteries
    David Baker, BOPS


10:00-12:00 Accelerator Architecture
Session Chair: Tom Conte (North Carolina State University)


    Two-level Hierarchical Register File Organization for VLIW
    Processors
    Javier Zalamea, Josep Llosa, Eduard Ayguade, Mateo Valero
    (Universitat Politècnica de Catalunya)


    PipeRench Implementation of the Instruction Path Coprocessor
    Yuan Chou, Pazhani Pillai, Herman Schmit, John P Shen (Carnegie
    Mellon University)


    Efficient Conditional Operations for Data-Parallel Architectures
    Ujval J Kapasi, William J Dally, Scott Rixner, Peter R Mattson,
    John D Owens, Brucek Khailany (Stanford University)


    Flexible Hardware Acceleration for Multimedia Oriented
    Microprocessors
    Frederik Vermeulen, Lode Nachtergaele, Francky Catthoor, Diederik
    Verkest, Hugo De Man (Katholieke Univ. Leuven)


12:00-13:30 Lunch


13:30-15:30 Low-Power Design
Session Chair: Rajiv Gupta (University of Arizona)


    Very Low Power Pipelines using Significance Compression
    Ramon Canal, Antonio Gonzalez (Universitat Politècnica de
    Catalunya), James E Smith (University of Wisconsin - Madison)


    A Static Power Model for Architects
    Jeffrey A Butts, Guri Sohi (University of Wisconsin -Madison)


    A Framework for Dynamic Energy Efficiency and Temperature Management
    Wei Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas (University
    of Illinois at Urbana-Champaign)


    Dynamic Zero Compression for Cache Energy Reduction
    Luis Villa, Zhang Michael, Krste Asanovic (MIT)


16:00-18:00 Memory Hierarchy II
Session Chair: Mike Smith (Harvard University)


    Register Integration: A Simple and Efficient Implementation of
    Squash Re-Use
    Amir Roth, Gurindar S Sohi (University of Wisconsin - Madison)


    The Store-Load Address Table and Speculative Register Promotion
    Matthew A Postiff, David A Greene, Trevor N Mudge (University of
    Michigan)


    Memory Hierarchy Reconfiguration For Energy and Performance In
    General-Purpose Processor Architectures
    Rajeev Balasubramonian, David Albonesi, Alper Buyuktosunoglu,
    Sandhya Dwarkadas (University of Rochester)


    Frequent Value Compression in Data Caches
    Jun Yang, Youtao Zhang, Rajiv Gupta (University of Arizona)


Wednesday Dec. 13, 2000


8:00-10:00 Dynamic Translation and Multithreading
Session Chair: Kemal Ebcioglu (IBM)


    A Study of Slipstream Processors
    Zachary Purser, Karthik Sundaramoorthy, Eric Rotenberg (North
    Carolina State University)


    Relational Profiling: Enabling Thread Level Parallelism in Virtual
    Machines
    Timothy H Heil, James E Smith (University of Wisconsin - Madison)


    Calpa: A Tool for Automating Selective Dynamic Compilation
    Markus U Mock, Craig Chambers, Susan J Eggers (University of
    Washington)


    Increasing the Size of Atomic Instruction Blocks by using Control
    Flow Assertions
    Sanjay J Patel, Tony Tung, Satarupa Bose, Matthew Crum (University
    of Illinois at Urbana-Champaign)


10:30-12:30 Superscalar Architecture
Session Chair: Bob Colwell (Intel)


    Reducing Wire Delay Penalty through Value Prediction
    Joan-Manuel Parcerisa, Antonio González (Universitat Politècnica de
    Catalunya)


    Compiler Controlled Value Prediction using Branch Predictor Based
    Confidence
    Eric Larson, Todd Austin (University of Michigan)


    Instruction Distribution Heuristics for Quad-Clustered, Dynamically-
    Scheduled Superscalar Processors,
    Amirali Baniasadi (Northwestern University), Andreas Moshovos
    (University of Toronto)


    Performance Improvement with Circuit-Level Speculation
    Tong Liu, Shih-Lien Lu (Intel)


12:30-13:00 Closing and Awards


14:30-18:00 Tutorial


    Dynamic Binary Translation and Optimization
    Erik Altman, Kemal Ebcioglu (IBM)


Conference Chairs
General: Andy Wolfe (S3)
Program: Mike Schlansker (Hewlett-Packard)
Finance: Tom Conte (North Carolina State University
Publication: Kevin Skadron (University of Virginia)
Publicity: Scott Mahlke (Hewlett-Packard)
Workshops/Tutorials: Chris Newburn (Intel)
Steering Committee
Rich Belgard (Consultant)
Tom Conte (North Carolina State University)
Kemal Ebcioglu (IBM)
Wen-mei Hwu (University of Illinois)
Yale Patt (University of Texas at Austin)
Ronny Ronen (Intel Israel)
Jim Smith (University of Wisconsin)
Program Committee
Pradip Bose (IBM)
Bob Colwell (Intel)
Tom Conte (North Carolina State University)
Henk Corporaal (Delft University)
Jim Dehnert (SGI)
Kemal Ebcioglu (IBM)
Joel Emer (Compaq)
Keith Farkas (Compaq)
Rajiv Gupta (University of Arizona)
Wen-Mei Hwu (University of Illinois)
Lizzy John (University of Texas at Austin)
Richard Johnson (Transmeta)
Roy Dz-Ching Ju (Intel)
Vinod Kathail (Hewlett-Packard)
Bill Mangione-Smith (UCLA)
Hans Mulder (Intel)
Yale Patt (University of Texas at Austin)
Ronny Ronen (Intel Israel)
Andre Seznec (IRISA/INRIA)
Jim Smith (University of Wisconsin)
Mike Smith (Harvard University)
Guri Sohi (University of Wisconsin)
Lothar Thiele (ETH Zurich)
Carol Thompson (Hewlett-Packard)
Gary Tyson (University of Michigan)
Mateo Valero (UPC Barcelona)
Pen-Chung Yew (University of Minnesota)

Return to the comp.compilers page.
Search the comp.compilers archives again.