Re: Branch prediction (was: eliminating array bounds checking overhead)

  Patryk Zadarnowski <patrykz@ilion.eu.org> writes:
> I've read somewhere that many post-pentium CPUs incur a
>10-20 clock cycle penalty for mispredicted branches (don't quote me on
>that).


Yes, in the P6 has the execute stage is stage 10, and branch
prediction is resolved there (at the earliest); the result of this
resolution is needed in stage 1. The branch may also have to wait in
reservation station until its data dependences are resolved, which
increases the penalty even more.


[backward taken/forward not taken]
>The scheme you mention has been used on plain pentiums,


The Pentium uses a 512-entry BTB, with every entry also containing a
two-bit counter for predicting the direction (with a flaw that was
fixed in the Pentium MMX). This was probably the most advanced branch
predictor of its time and the BTB is still state-of-the-art for
predicting indirect branches today (better schemes have been proposed
in research papers, though).


Crossposted and followups set to comp.arch


- anton
--
M. Anton Ertl Some things have to be seen to be believed
anton@mips.complang.tuwien.ac.at Most things have to be believed to be seen
http://www.complang.tuwien.ac.at/anton/home.html

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