Compiler positions available for week ending February 27

This is a digest of ``help wanted'' and ``position available'' messages
received at comp.compilers during the preceding week. Messages must
advertise a position having something to do with compilers and must also
conform to the guidelines periodically posted in misc.jobs.offered.
Positions that remain open may be re-advertised once a month. To respond
to a job offer, send mail to the author of the message. To submit a
message, mail it to compilers@iecc.com.




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From: John Zhong <zhong@innologic-systems.com>
Subject: Position Available in an EDA company
Date: Wed, 23 Feb 2000 11:12:33 -0800
Organization: Innologi Systems, Inc.
Reply-To: zhong@innologic-systems.com


InnoLogic Systems, Inc. is a start up developing symbolic Verilog
(Hardward Description Language) simulator for design verification.
InnoLogic's flagship products are based on innovative symbolic
simulation/manipulation techniques in all levels of Verilog language
constructs including behavioral level (such as for/while-loop, wait
and other concurrent, non-synthesizable constructs), RT level and
switch level. We believe that the technology offers a new approach to
parallel/high performance simulation and even to the high performance
general computing.


InnoLogic's customers are design/semiconductor companies. The
company's customers include MIPS Technoglogy, SGS Thomson, Philips,
Transmeta, Quantum Effect Devices and others.


We are looking for bright and motivated people to develop our
back-end/front-end compiler and runtime kernels. The following is the
detailed description.


=====


Position 1: Simulation and back end compiler optimization


Job Description: Responsible for high performance back end compilation
and/or simulation kernel. Work as part of the core development team
for symbolic simulation products.


Skills: MSCS/MSEE or equivalent required. Experienced in back end
optimization for a programming language and/or HDL compiler. Exprienced
in an industrial strength Unix/C/C++ development environment. Highly
competent in graph/optimization algorithms. Experience in EDA/Verilog
simulators/formal verification is a plus.


Position 2: Symbolic switch/circuit simulation


Job Description: responsible for ESP-CV development. Work as part of
the core team to design and develop the product.


Skills: MSCS/MSEE or equivalent required. Exprienced in an industrial
strength Unix/C/C++ development environment. Familiar with Spice
and/or Verilog switch level language. Experienced with language
parsing techniques (including Lex/Yacc). Knowledge of full custom
circuit design and formal verification techniques is highly preferred.


=====


Contact:
John Zhong
V.P. Engineering
InnoLogic Systems, Inc.
2860 Zanker Road, Suite 203
San Jose, CA 95134
Tel: 408-432-6188 ext 108
Fax: 408-432-6187
zhong@innologic-systems.com
www.innologic-systems.com


-------------------------------


From: "Kirk Macolini" <kirk@grammatech.com>
Subject: Compiler job at Grammatech, Ithaca NY
Date: Fri, 25 Feb 2000 12:24:00 -0500


As a result of our recent successes, GrammaTech (www.grammatech.com)
has 4-8 immediate openings for technical people. We need people at
all levels (BS, MS, PhD) --- preferably people who can walk on water
and are allergic to California.


Our R&D projects include:


* Dependence Graphs for Information Assurance of Systems (DARPA/IASET, in
negotiation)
--- Goals:
(1) SystemSurfer: Adaptation and extension of our present technology to
address heterogeneous system models involving UML models, code, and HDL
hardware descriptions.
(2) Information Assurance Workbench: an application layer addressing
specific IA questions that can be answered using dependence graphs.
URL: http://www.if.afrl.af.mil/div/IFT/IFTD/iaset/ia16.html


* Multi-lingual Dependence-Graphs Components for Hardware and Software
Analysis, Design, and Specialization (DARPA/SBIR Phase II)
--- Goals:
(1) scale our present program-slicing and code-surfing technology to 1M SLOC
(2) adapt it for C++
(3) improve its precision with better pointer analysis and fine-grain
dependence analysis
URL: http://www.grammatech.com/products/codesurfer/codesurfer.html


* Model Checking of Software Designs (ONR)
--- Goal: formal verification of Rose/Real Time models


So we need people knowledgeable about compilers (front ends,
intermediate representations, static program analysis, abstract
interpretation, data flow analysis, etc.), concurrency, program
slicing, environments and GUI programming, model checking, security,
and UML. We also need generalists skilled at Windows and UNIX
programming.


GrammaTech is located in Ithaca, New York. Ithaca offers the best of
two worlds: a vibrant cultural community surrounded by peaceful
countryside. Ithaca is home to Cornell University and Ithaca College.
Located at the southern tip of 40-mile long Cayuga Lake, Ithaca is in
the heart of central New York's scenic Finger Lakes Region. Residents
enjoy high quality of life with easy access to entertainment and
recreation including theatre, music, museums, wineries, farmers'
markets, sailing, hiking, and skiing.


If you are interested in opportunities at GrammaTech, send your resume
and availability to admin@grammatech.com


[Grammatech is right down the road from me, their projects look pretty
interesting. But in my role as Sewer Commissioner I'm not sure how I
feel about the walking on water part. -John]

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