What Chips Support Which Exceptions? A Survey

Steve Stevenson <steve@wayne.cs.clemson.edu>
24 Jul 1998 12:35:40 -0400

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What Chips Support Which Exceptions? A Survey steve@wayne.cs.clemson.edu (Steve Stevenson) (1998-07-24)
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From: Steve Stevenson <steve@wayne.cs.clemson.edu>
Newsgroups: comp.arch,comp.arch.arithmetic,comp.compilers
Followup-To: comp.arch.arithmetic
Date: 24 Jul 1998 12:35:40 -0400
Organization: Clemson University
Keywords: arithmetic, question, architecture

While the arrival of the IEEE floating point standards have gone a
long way towards making life easier for numerical programming, we have
a *long* way to go. Kahan has continued to sound the alarm on how
slowly the manufacturers are coming into compliance. But there is
another even more insidious situation: exceptions. While IEEE states
the floating point exceptions (the situation is not so wonderful as
you might expect), there is no similar guarantee with *integer*
exceptions. The problem with integer exceptions is not new news but
there is no catalog of what chips support what.

I am trying to develop such a catalog. The survey is found on


If you have experience/knowledge about "comodity" chips (no matter how
exotic/erotic), would you please check the site and help me collect
the information.

Best regards,

Steve (really "D. E.") Stevenson Assoc Prof
Department of Computer Science, Clemson, (864)656-5880.mabell
Homepage: http://www.cs.clemson.edu/~steve/
Wanted: Sterbenz, P. Floating Point Computation

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