|GCC Register Allocator email@example.com (Andrea Vettori) (1998-01-17)|
|From:||Andrea Vettori <firstname.lastname@example.org>|
|Date:||17 Jan 1998 00:04:24 -0500|
|Organization:||Universita' degli studi di Padova - Dipartimento di Elettronica e Informatica|
|Keywords:||GCC, registers, optimize|
Looking to assembly code produced by GCC (HPUX on PA-RISC, version
2.7.2) I found that the register allocator reuses as early as possible
the same temporary registers (am I wrong ??). I know that this is
useful for spilling but what about processors that do speculation
without register renaming ?
For my Laurea degree thesis, I'm looking at optimizations that improve
the parallelism of code. Renaming manually the registers and
rescheduling the code (with a global scheduling algorithm) of my
primary test-case (a Full Search Block Matching algorithm) I can get
near 20% improvement on running time on a standard (non speculative)
superscalar processor. It seems to me that even using a basic block
scheduler, the improvement can reach 5-7 %.
After my opinions comes my question :)
Is there a (easy) method to tell GCC to use the temporary registers as a
queue instead of a stack ?
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