Euro-Par'97 ILP Workshop (Robert Mullins)
14 Jan 1997 20:19:46 -0500

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Euro-Par'97 ILP Workshop (1997-01-14)
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From: (Robert Mullins)
Newsgroups: comp.arch,comp.compilers
Date: 14 Jan 1997 20:19:46 -0500
Organization: Department of Computer Science, University of Edinburgh
Keywords: conference, CFP, parallel, architecture

                                      Euro-Par'97 Workshop

                            Instruction-Level Parallelism

Program Committee:

Chris Jesshope, Massey University, New Zealand, Global Chair
Damal K.Arvind, University of Edinburgh, UK, Local Chair
Kemal Ebcioglu, IBM Watson, USA, Vice-Chair
Michael Schlansker, Hewlett-Packard, USA, Vice-Chair
Michael Smith, Harvard University, USA, Vice-Chair

Deadline: 20 January 1997(paper); 1 February 1997(electronic)

Euro-Par is the annual European conference in Parallel Processing.
Like the 1996 conference in Lyon, the 1997 version will consist of a
number of highly focused workshops on all aspects of parallel
processing, from theory to practice, from academy to industry. The
workshops will present the latest advances in their respective
domains. In addition, there will be a number of high-level tutorials
of general interest plus a series of invited talks. Calls for papers
for 20 workshops are being launched. All accepted papers will appear
in the proceedings published by Springer-Verlag in the LNCS Series.

Workshop #17: Instruction-Level Parallelism. Instruction-level
parallelism (ILP) is now the norm in modern microprocessor devices
using one or more of the following techniques: superscalar,
superpipelining, VLIW and multi-threading. The goal of course is to
increase the throughput of a computational device by issuing more than
a single instruction in a single clock period. There are many
implications from these developments in microprocessor architecture
ranging from pure design optimisations to compilation techniques.
Indeed, many of these issues are interdependent and cannot be
considered in isolation. This workshop is intended to present a forum
for researchers and developers in this field to discuss and debate key
issues of common interest.

Topics of interest include:

          memory hierarchy and latency
          performance analysis
          asynchronous architectures for ILP
          compilation and optimisation
          speculation vs. threading
          dynamic vs. static scheduling

Further information is available here. It includes the list of all
workshops. Please send all information requests and comments to Register today on the Euro-Par'97 mailing
list by sending us a mail! See below for the official conference

          Euro-Par'97, Universitdt Passau, D-94030 Passau, Germany
            Phone: (+49) (851) 509-3071; Fax: (+49) (851) 509-3092

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