|Workshop on Interaction between Compilers and Computer Architectures email@example.com (Sangyeun Cho) (1997-01-03)|
|From:||Sangyeun Cho <firstname.lastname@example.org>|
|Date:||3 Jan 1997 23:16:05 -0500|
|Organization:||Univ. of Minnesota|
F I N A L P R O G R A M
Workshop on Interaction between
Compilers and Computer Architectures
(Feb. 1 1997, San Antonio TX)
I. Architecures (4 papers) 8:30 - 10:00 a.m.
. Issues in Compilation for Fixed-Length Block Structured
Instruction Set Architectures
Henk Neefs, Koen De Bosschere and Jan Van Campenhout
University of Gent, Gent, Belgium
. A Compiler Perspective on Architectural Evolutions
Nicholas Mitchell, UCSD
Larry Carter, UCSD and San Diego Supercomputing Center
Jeanne Ferrante, UCSD
. Compiler/architecture interaction in a tree-based
M. Moudgill, J. H. Moreno, K. Ebcioglu, E. Altman
S. K. Chen, and A. Polyak
IBM T. J. Watson Research Center
. Branch Decoupled Architectures
CS Dept., Iowa State University
II. Optimizations (5 papers) 10:20 a.m. - 12:00 p.m.
. Interactions between Application Write Performance and
Compilation Techniques: A Preliminary View
Margaret Martonosi, Princeton Univ., and
Kelly Shaw, Duke Univ.
. Procedure Mapping Using Static Call Graph Estimation
A. H. Hashemi, D. R. Kaeli, and B. Calder
Northeastern Univ. and UCSD
. FMAC Code Optimization Issues
William Blume and Wei-Chung Hsu
Hewlett Packard Company
. Optimizing Out-of-Core Computations in Uniprocessors
M. Kandemir, CIS Dept., Syracuse Univ.
A. Choudhary, ECE Dept., Northwestern Univ.
J. Ramanujam, ECE Dept., Lousiana State Univ.
R. Bordawekar, CACR, Caltech
. Compiler-aided loop speed-up opportunities in High-End
PowerPC (TM) Processors
Pradip Bose and John-David Wellman
IBM T. J. Watson Research Center
III. Instruction Sceduling and Parallelism (6 papers) 1:00 - 3:00 p.m.
. Intelligent Loop Unrolling
Lacky Shah, Hewlett Packard Company
. GNU Instruction Scheduler: Ailments and Cures in Context of Superscalarity
Andreas UNGER and Eberhard ZEHENDNER
Inst. f. Informatik
Fak. f. Math./Inf.
Friedrich-Schiller-Univ., Jena, GERMANY
. Global Instruction Scheduling in Machine SUIF
Gang Chen and Mike Smith
. Parallel Static Single Assignment Form and Constant
Propagation for Explicitly Parallel Programs
Jaejin Lee and David Padua
CS Dept., Univ. of Illinois at Urbana-Champaign
. Parallelizing OO Programs: Precise Call-Graph in the Presence of
Deepankar Bairagi, Sandeep Kumar, and Dharma P. Agrawal
Dept. of Electrical and Computer Engineering
North Carolina State Univ.
. VLIW-Style Parallelism On Aggregate Function Clusters
Soohong P. Kim and Henry G. Dietz
School of Electrical and Computer Engineering
IV. Cache Memory (5 papers) 3:20 - 5:00 p.m.
. Prefetch Hardware Support for cache Coherence Enforcement:
Design Cosiderations and Potential Performance
Hock-Beng Lim, CS Dept., Univ. of Illinois at Urbana-Champaign, and
Pen-Chung Yew, CS Dept., Univ. of Minnesota
. Cache Miss Equations: An Analytical Representation of Cache Misses
Somnath Ghosh, Margaret Martonosi, and Sharad Malik
EE Dept., Princeton Univ.
. Accurate data distribution into blocks may boost cache performance
Dan Truong, Andre Seznec, and Francois Bodin
IRISA / INRIA (France)
. Estimation of Cache Parameters and number of registers based on
Changwoo Pyo, Hong-Ik Univ., Seoul, Korea, and
Gyungho Lee, UTSA
. c_ICE: A Compiler-based Instruction Cache Exclusion Scheme
L. John and R. Radhakrishnan, Univ. of Texas at Austin
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