|made up byte code: registers vs. literals email@example.com (1996-11-24)|
|Re: made up byte code: registers vs. literals firstname.lastname@example.org (Ray S. Dillinger) (1996-12-01)|
|Re: made up byte code: registers vs. literals email@example.com (1996-12-03)|
|Re: made up byte code: registers vs. literals firstname.lastname@example.org (Russell Bornsch++) (1996-12-03)|
|From:||Russell Bornsch++ <email@example.com>|
|Date:||3 Dec 1996 20:57:58 -0500|
jon klein wrote:
: The interpreter has a couple of virtual registers to store intermediate
: results. The was I'm doing it, each 8-bit operator has 3 8-bit operands,
: so that each instruction is 32 bits wide.
: ADD %r1,%r2,%r3 ; r3 = r1 + r2
Ray S. Dillinger wrote:
> Right, a 3-address code; not real efficient for space, but very flexible.
: The problem deals with literals. Say I want to:
: ADD 5, %r2, %r3
: or the more important problem
: MOV 10, %r1
: The general question then, is: how does the Sparc (or any... I'm just
: familiar with Sparc) assembler handle this?
> I can't speak to the sparc, but the way most assemblers handle it is that
> there are different opcodes for operations on literals than for operations
> on registers. The assembler tries to 'hide' this fact from you to make
> the language easier to conceptualize. But when you write
> ADD %3 %5 %2
> the assembler uses a different add instruction than when you write
> ADD 3 %5 %2
In some architectures that support register indirect mode with post-
increment (I think maybe PDP-11?), a literal is implemented by treating
the program counter as "just another address register":
Conceptually, the instruction is fetched, the PC incremented to point
to the non-executable data word, the instruction is decoded, the data
word is loaded and stuffed into %r1, and PC is incremented to point
to the following instruction.
Obviously you would like the assembler to recognize a shorthand for
Some sick part of me finds this really elegant. Note that a jump
therefore becomes simply a move to the PC; a call is a "push PC"
(which is itself probably a register indirect with predecrement...)
followed by a move to PC. All very orthogonal.
Of course, you *still* need some bits in the opcode to indicate
register direct versus indirect versus indirect with pre/post/inc/dec
options, which returns us to Bear's answer.
[This all worked on the PDP-11, but it's my impression that to pipeline an
implementation, they had to treat the in-line values and PC references as
special cases anyway. -John]
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