|Workshop on Embedded HPC Systems and Applications (EHPC'97) firstname.lastname@example.org (1996-10-06)|
|From:||email@example.com (Devesh Bhatt)|
|Date:||6 Oct 1996 17:07:35 -0400|
|Posted-Date:||Sun, 6 Oct 96 15:47:10 CDT|
Call for Participation
2nd International Workshop on
Embedded HPC Systems and Applications (EHPC'97)
April 5, 1997, University of Geneva, Geneva, Switzerland
at the 11th IEEE International Parallel Processing Symposium (IPPS'97)
The International Workshop on Embedded HPC Systems and Applications
(EHPC) is a forum for the presentation and discussion of approaches,
research findings, and experiences in the applications of High
Performance Computing (HPC) technology for embdded systems. Of
interest are both the development of relevant technology (e.g.:
hardware, middleware, tools) as well as the embedded HPC applications
built using such technology.
We hope to bring together industry, academia, and government
researchers/users to explore the special needs and issues in applying
HPC technologies to defense and commercial applications.
Topics to be considered in EHPC'97 include:
-- Algorithms and Applications: addressing parallel computing needs of
applications such as radar signal processing, surveillance, automated
target recognition, etc.
-- Programming Environments: addressing software design,
programming/parallelization methods, and development tools.
-- Complex Systems Engineering: addressing performance modeling/simulation,
partitioning/mapping and architecture trade-off, system integration,
debugging and testing tools.
-- Operating Systems and Middleware Services: addressing real-time
scheduling, fault-tolerance, and static/dynamic resource management needs
of embedded applications.
-- Architectures: addressing special-purpose processors, high-performance
packages, and advanced vision systems.
The workshop will feature technical presentations, a keynote speech,
and an open discussion session. The proceedings of the workshop will
be made available on the web.
Authors are invited to submit by email a 5-page extended abstract of
their presentation to Devesh Bhatt (firstname.lastname@example.org, +1
612-951-7316) by Nov. 22 1996. Extended abstracts must be either in
plain ascii or postscript format. If submitting in postscript, please
include the title, authors, and affiliation in plain ascii text
also. Submissions will be reviewd by the program committee.
Acceptance notifications will be made by January 15 1997. Camera ready
postscript files are due by March 15, 1997. Proceedings will be
published on the World-Wide Web. Only abstracts will be distributed in
hard-copy to the workshop attendees.
Devesh Bhatt, Honeywell Technology Center, USA (email@example.com)
Viktor Prasanna, Univ. of Southern California, USA (firstname.lastname@example.org)
Ashok Agrawala, Univ. of Maryland, USA
Milissa Benincasa, Rome Laboratory, USA
Clive Benjamin, Wright Laboratory, USA
Bob Bernecky, NUWC, USA
Terry Fountain, University College London, UK
Richard Games, MITRE, USA
Farnam Jahanian, Univ. of Michigan, USA
Craig Lund, Mercury Computer Systems, Inc., USA
David Martinez, MIT Lincoln Laboratory, USA
Rick Metzger, Rome Laboratory, USA
Stephen Rhodes, Adavanced Systems Architectures Ltd., UK
Philip Sementilli, Hughes Missile Systems Co., USA
Anthony Skjellum, Mississipi State Univ., USA
Lothar Thiele, Swiss Federal Institute of Technology, Zuerich, Switzerland
Chip Weems, Univ. of Massachusetts, USA
Sudhakar Yalamanchili, Georgia Tech., USA
Keith Bromley, NRaD, USA
Dieter Hammer, Eindhoven Univ. of Technology, The Netherlands
Jose Munoz, DARPA/ Information Technology Office, USA
Clayton Stewart, SAIC, USA
Lonnie Welch, Univ. of Texas at Arlington, USA
This workshop is being held as part of IPPS. The usual IEEE Computer
Society guidelines apply wrt registration. Information about IPPS can be
obtained over the Web at the following URL:
Return to the
Search the comp.compilers archives again.